Datasheet
PowerPC 970FX RISC Microprocessor
4.2.2.1 Mechanical Specifications
The solder balls on the bottom of the reduced-lead package are slightly smaller, which will decrease the
overall module height when assembled onto a system board. Heatsink solutions should be modified accord-
ingly
.
Table 4-1. Standard-Lead and Reduced-Lead Package, Layout, and Assembly Differences
JEDEC
Moisture
Sensitivity
Level (MSL)
CBGA
Card Solder
Solder Ball
Diameter
mm (inch)
Card Solder
Screen
Diameter
Card Pad
Diameter
mm (inch)
Solder Ball
Composition
Substrate I/O Mask Opening
Pad Diameter
mm (inch)
Package
Diameter
mm (inch)
26.5 mil open-
ing in 7.5 mil
thick stencil,
2500-4600
Sn 10%
Pb 90%
Standard Lead
Reduced Lead
1
3
0.80 (0.0315)
0.635 (0.025)
0.80 (0.0315)
0.80 (0.0315)
0.80 (0.0315)
0.72 (0.028)
0.70 (0.0275)
0.61 (0.024)
cubic mils
23 mil opening
in 4 mil thick
stencil, 1400-
2000 cubic mils
Sn 95.5%
Ag 3.8%
Cu 0.7%
Note: All dimensions in mm unless noted. Dimensions in parenthesis are in inches.
4.2.2.2 Assembly Considerations
The reduced-lead package is compatible with a 260°C lead-free card assembly reflow profile. See the Inter-
national Electronics Manufacturing Initiative (iNEMI) Consortium, www.inemi.org, for industry-standard
assembly and rework information. The coplanarity specification for the reduced-lead CBGA, like other single
melt BGA packages, is 0.20 mm (8 mil). The qualification testing included a lead-free, water-soluble solder
paste with type 3 mesh size (-325 500). The solder alloy is 95.5% Sn, 4.0% Ag, and 0.5% Cu, with a 90%
metal loading. The paste viscosity range is 600 to 800 thousands of centipoises (kcps). The thickness of the
stencil is 4 mils and the aperture diameter is 23 mils. The target solder paste volume range is between 1400
to 2000 cubic mils. Achieving the correct paste volume is necessary to eliminate solder shorts and produce
high reliability solder joints. The actual solder paste volume from the qualification build ranged from 1750 to
2000 cubic mils.
The JEDEC moisture sensitivity level is MSL 3 for the reduced-lead package. Storage and assembly proto-
cols should be modified accordingly.
Figure 4-4 on page 50 and Figure 4-5 on page 51 show the side and top views of the packages including the
height from the top of the die to the bottom of the solder balls. Figure 4-6 on page 52 shows a bottom view of
the PowerPC 970FX.
Version 2.5
Dimensions and Physical Signal Assignments
Page 49 of 78
March 26, 2007
IBM [ IBM ]
