PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Thermal Sensor Specifications
See System Design Section.
DC Electrical Specifications
See ”Recommended Operating Conditions,” on page 11, for operating conditions.
Characteristic
Symbol
VIH(3.3V)
VIH(2.5V)
VIH()1.8V
VIL(3.3V)
VIL(2.5V)
VIL()1.8V
CVIH(3.3V)
CVIH(2.5V)
CVIH(1.8V)
CVIL
Min
2.0
1.75
1.4
GND
GND
GND
2.0
2.0
1.5
–
Max
3.465
2.625
1.89
0.8
Unit
V
Notes
1, 2
Input high voltage (all inputs except SYSCLK)
Input low voltage (all inputs except SYSCLK)
SYSCLK input high voltage
V
V
0.7
0.5
3.465
2.625
1.89
0.4
1, 4
SYSCLK input low voltage
V
µA
µA
V
4
Input leakage current, VIN = OVDD
Hi-Z (off state) leakage current, Vin = OVDD
Output high voltage, IOH = –6mA
Output high voltage, IOH = –6mA
Output high voltage, IOH = –3mA
Output low voltage, IOL = 6mA
Capacitance, VIN =0 V, f = 1MHz
Note:
IIN
–
20
1, 2
1, 2
ITSI
–
20
VOH(3.3V)
VOH((2.5V))
VOH(1.8V)
VOL
2.4
1.9
1.4
–
–
–
V
–
V
0.4
V
CIN
–
5.0
pF
2,3
1. For 60x bus signals, the reference is OVDD, while L2OVDD is the reference for the L2 bus signals.
2. JTAG port signal levels are controlled by the BVSEL pin and are the same as those shown for the 60x bus. LSSD_MODE, L1_TSTCLK, and L2TSTCLK
receiver voltage levels are those shown for OVDD = 1.8V nominal, regardless of BVSEL. JTAG, LSSD_MODE, L1_TSTCLK, and L2TSTCLK values in
this table are guaranteed by design and characterization, and are not tested.
3. Capacitance values are guaranteed by design and characterization, and are not tested.
4. SYSCLK input high and low voltage: I/O timings are measured using a “rail to rail” SYSCLK; I/O timing may be less favorable if SYSCLK does not travel
from GND to OVDD
.
9/6/2002
Version 2.0
Page12
IBM [ IBM ]
