PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
L2 Bus Output AC Specifications
L2 Bus Output Interface AC Timing Specifications1
See ”Recommended Operating Conditions,” on page 11 for operating conditions, C = 20pF .
3
L
Num
Characteristic
L2CR[14:15] is equivalent to:
01 10
Unit
ns
Notes
2
11
Max
00
Min
—
Max
3.2
Min
—
Max
Min
—
Max
Min
—
5
5
26
L2SYNC_IN to output valid,
3.7
Rsv
Rsv
7
Fmax up through 375 MHz.
5
5
5
5
5
5
26
26
26
L2SYNC_IN to output valid, Fmax
= 400 MHz.
—
—
—
3.0
2.6
2.4
—
—
—
3.5
3.1
2.9
—
—
—
—
—
—
ns
ns
ns
Rsv
Rsv
Rsv
Rsv
Rsv
Rsv
L2SYNC_IN to output valid, Fmax
= 433 and 450 MHz.
L2SYNC_IN to output valid, Fmax
= 466 and above.
5
5
27
28
L2SYNC_IN to output hold
0.5
—
—
1.0
—
—
—
—
ns
ns
4, 6
6
Rsv
—
Rsv
—
5
5
L2SYNC_IN to high impedance
3.5
4.0
Rsv
Rsv
Note:
1. All outputs are measured from the Vm of the rising edge of L2SYNC_IN to the Vm of the signal in question. The output timings are measured at the pins
(see Figure 9).
2. The outputs are valid for both single-ended and differential L2CLK modes. For flow-through and pipelined reg-reg synchronous burst SRAMs,
L2CR[14:15] = 00 is recommended. For pipelined late-write synchronous burst SRAMs, L2CR[14:15] = 01 is recommended.
3. All maximum timing specifications assume C = 20pF.
L
4. This measurement assumes C = 5pF.
L
5. Reserved for future use.
6. Guaranteed by design and characterization, and not tested.
7. Specifications are shown as a Function of Maximum Core Frequency (Fmax). They refer to the effective Fmax of the part after derating for application
conditions. For example, a nominal 450 MHz part running at application conditions that derate its Fmax to 400 MHz will meet or exceed the specifica-
tions shown for Fmax = 400 MHz.
Page 23
Version 2.0
9/6/2002
IBM [ IBM ]
