PowerPC 750 SCM RISC Microprocessor
PID8p-750
Preliminary Copy
5
Pinout Listing for the 360 CBGA package
Signal Name
PLL_CFG[0-3]
QACK
Pin Number
Active
High
Low
Low
Low
Low
Low
—
I/O
Input
Input
Output
Output
Input
Input
Input
Input
Input
I/O
A4, A5, A6, A7
B2
QREQ
J3
RSRV
D3
SMI
A12
E10
H9
SRESET
SYSCLK
TA
F1
Low
High
Low
High
TBEN
A2
TBST
A11
B10
7
Input
TCK
TDI
B7
High
High
Low
Low
High
Low
Low
High
High
Low
—
Input
Output
Input
Input
Input
Input
I/O
TDO
D9
TEA
J1
TLBISYNC
TMS
A3
C8
TRST
TS
A10
K7
TSIZ0-TSIZ2
TT0-TT4
WT
A9, B9, C9
Output
I/O
C10, D11, B12, C12, F11
C3
Output
—
2
G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12
VDD
3
K13
W1
High
—
Output
Input
VOLTDET
BVSEL6
L2VSEL6
A19
—
Input
Note:
1. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.
2. OVDD inputs supply power to the I/O drivers and VDD inputs supply power to the processor core.
3. Internally tied to L2OVDD in the PID8p-750 360 CBGA package. This is NOT a supply pin.
4. These pins are reserved for potential future use as additional L2 address pins.
5. Pull up and pull down resistor requirements for all pins are listed in the “Pull-up / Pull-down Resistor Requirements” section on page 33
6. BVSEL selects the I/O voltage on the 60X bus. L2VSEL selects the I/O voltage on the L2 bus. Please refer to the Table “Recommended Operating
Conditions1,2,3,” on page 6, for the use of these pins.
7. TCK must be tied high or low for normal machine operation.
8. Address and data parity signals must be tied high or low if unused in the design.
9. Starting with rev levels dd3.X, the AVDD pin is no longer brought out to the package.
Page 26
Version 2.0
Datasheet
9/30/99
IBM [ IBM ]
