PowerPC 750 SCM RISC Microprocessor
PID8p-750
Preliminary Copy
Overview
The PID8p-750 is targeted for high performance, low power systems and supports the following power man-
agement features: doze, nap, sleep, and dynamic power management. The PID8p-750 consists of a proces-
sor core and an internal L2 Tag combined with a dedicated L2 cache interface and a 60x bus.
Figure 1 shows a block diagram of the PID8p-750.
Figure 1. PID8p-750 Block Diagram
Control Unit
Instruction Fetch
Branch Unit
Completion
32K ICache
BHT /
BTIC
System
Dispatch
Unit
GPRs
FPRs
FXU2
LSU
FPU
FXU1
Rename
Buffers
Rename
Buffers
32K DCache
L2 Tags
L2 Cache
BIU
60X
BIU
Page 2
Version 2.0
Datasheet
9/30/99
IBM [ IBM ]
