.
DD 2.X
Preliminary
PowerPC 750FX RISC Microprocessor
1. General Information
®
The IBM PowerPC 750FX RISC Microprocessor is a 32-bit implementation of the IBM PowerPC family of
reduced instruction set computer (RISC) microprocessors. This document contains pertinent physical and
electrical characteristics of the IBM PowerPC 750FX RISC Microprocessor Revision DD 2.X Single Chip
Modules (SCM). The IBM PowerPC 750FX RISC Microprocessor is also referred to as the 750FX throughout
this document.
1.1 Features
This section summarizes the features of the 750FX
implementation of the PowerPC Architecture™.
Major features of the 750FX include the following:
• Dispatch unit
– Full hardware detection of dependencies
(resolved in the execution units)
– Dispatch two instructions to six independent
units (system, branch, load/store, fixed-point
unit 1, fixed-point unit 2, or floating-point)
– 4-stage pipeline: fetch, dispatch, execute,
and complete
• Branch processing unit
– Four instructions fetched per clock
– One branch processed per cycle (plus
resolving two speculations)
– Up to one speculative stream in execution,
one additional speculative stream in fetch
– 512-entry branch history table (BHT) for
dynamic prediction
– Serialization control (predispatch,
postdispatch, execution, serialization)
• Fixed-point units
– 64-entry, 4-way set associative branch
target instruction cache (BTIC) for
eliminating branch delay slots
– Fixed-point unit 1 (FXU1): multiply, divide,
shift, rotate, arithmetic, logical
– Fixed-point unit 2 (FXU2): shift, rotate,
arithmetic, logical
– Single-cycle arithmetic, shift, rotate, logical
– Multiply and divide support (multi-cycle)
– Early out multiply
• Decode
– Register file access
– Forwarding control
– Partial instruction decode
– Thirty-two 32-bit general purpose registers
• Load/store unit
• Floating-point unit
– One cycle load or store cache access (byte,
half-word, word, double-word)
– Effective address generation
– Hits under miss (one outstanding miss)
– Single-cycle misaligned access within
double-word boundary
– Alignment, zero padding, sign extend for
integer register file
– Floating-point internal format conversion
(alignment, normalization)
– Sequencing for load/store multiples and
string operations
– Store gathering
– Cache and TLB instructions
– Big and little-endian byte addressing
supported
– Support for IEEE-754 standard single and
double-precision floating-point arithmetic
– Optimized for single-precision multiply/add
– Thirty-two, 64-bit floating point registers
– Enhanced reciprocal estimates
– 3-cycle latency, 1-cycle throughput,
single-precision multiply-add
– 3-cycle latency, 1-cycle throughput,
double-precision add
– 4-cycle latency, 2-cycle throughput,
double-precision multiply-add
– Hardware support for divide
– Hardware support for denormalized
numbers
– Time deterministic non-IEEE mode
– Misaligned little-endian support in hardware
• System unit
– Executes CR logical instructions and mis-
cellaneous system instructions
– Special register transfer instructions
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
1. General Information
Page 3 of 63
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