Datasheet
DD 2.X
Preliminary
PowerPC 750FX RISC Microprocessor
1. General Information .................................................................................................... 3
1.1 Features ............................................................................................................................................ 3
1.2 Design Level Considerations and Features ...................................................................................... 5
1.3 Processor Version Register .............................................................................................................. 5
1.4 Part Number Information ................................................................................................................... 6
2. Overview ...................................................................................................................... 7
2.1 Block Diagram ................................................................................................................................... 7
2.2 General Parameters .......................................................................................................................... 8
3. Electrical and Thermal Characteristics ..................................................................... 9
3.1 DC Electrical Characteristics ............................................................................................................. 9
3.2 Clock AC Specifications .................................................................................................................. 13
3.3 Spread Spectrum Clock Generator (SSCG) ................................................................................... 14
3.5 60x Bus Output AC Specifications .................................................................................................. 17
3.6 Alternate I/O Timing For 3.3V Bus .................................................................................................. 19
3.6.1 IEEE 1149.1 AC Timing Specifications ................................................................................. 20
4. Dimensions and Signal Assignments ..................................................................... 22
4.1 Module Substrate Decoupling Voltage Assignments ...................................................................... 22
4.2 Package .......................................................................................................................................... 22
4.3 Microprocessor Ball Placement ....................................................................................................... 24
5. System Design Information ..................................................................................... 31
5.1 PLL Considerations ......................................................................................................................... 31
5.1.1 Restrictions and Considerations for PLL Configuration ......................................................... 32
5.1.1.1 Configuration Restriction on Frequency Transitions ...................................................... 32
5.1.2 PLL_RNG[0:1] Definitions for Dual PLL Operation ................................................................ 32
5.1.3 PLL Configuration .................................................................................................................. 33
5.2 PLL Power Supply Filtering ............................................................................................................. 35
5.3 Decoupling Recommendations ....................................................................................................... 39
5.4 Output Buffer DC Impedance .......................................................................................................... 42
5.4.1 Input-Output Usage ............................................................................................................... 43
5.5 Level Protection .............................................................................................................................. 48
5.6 64 or 32-Bit Data Bus Mode ............................................................................................................ 49
5.7 IIO Voltage Mode Selection ............................................................................................................ 49
5.8 Thermal Management ..................................................................................................................... 49
5.8.1 Heat Sink Selection Example ................................................................................................ 49
5.8.2 Internal Package Conduction ................................................................................................ 52
5.8.3 Minimum Heat Sink Requirements ........................................................................................ 53
5.8.4 Heat Sink Mounting ............................................................................................................... 54
5.8.5 Thermal Assist Unit ............................................................................................................... 54
5.8.6 Adhesives and Thermal Interface Materials .......................................................................... 55
5.8.7 Thermal Interface and Adhesive Vendors ............................................................................. 56
5.8.8 Heat Sink Vendors ................................................................................................................. 57
Revision Log ................................................................................................................ 59
750FX_DS_DD2.X_V2.02.fm.2.0
June 9, 2003
Page 1 of 63
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