DD 2.X
Preliminary
PowerPC 750FX RISC Microprocessor
3.5 60x Bus Output AC Specifications
Table 3-8 provides the 60x bus output AC timing specifications for the 750FX as defined in Figure 3-6 on
page 19.
Table 3-8. 60x Bus Output AC Timing Specifications
See Table 3-2 on page 10 for operating conditions.1, 5
1.8V
Min.
2.5V
Min.
3.3V
Min.
Num
12
Characteristic
Unit
ns
Notes
—
Max.
—
Max.
—
Max.
—
SYSCLK to Output Driven
(Output Enable Time)
0.3
0.3
0.3
13
14
SYSCLK to Output Valid
—
2.3
—
—
2.5
—
—
2.5
–
ns
ns
2, 6
2, 7
SYSCLK to Output Invalid (Output Hold)
0.5
0.55
0.55
SYSCLK to Output High Impedance
(all signals except ARTRY, ABB and DBB)
15
16
17
—
—
2.5
1.0
3.0
—
—
2.5
1.0
3.0
—
—
2.5
1.0
3.0
ns
—
3, 4
—
SYSCLK to ABB and DBB high impedance
after precharge
t
SYSCLK
SYSCLK to ARTRY high impedance
before precharge
—
—
—
ns
0.2×
0.2×
0.2×
18
SYSCLK to ARTRY precharge enable
Maximum delay to ARTRY precharge
t
+
t
+
—
t
+
—
ns
2, 3, 4
SYSCLK
SYSCLK
SYSCLK
1.0
1.0
1.0
19
20
—
—
1.0
2.0
—
1.0
2.0
—
1.0
2.0
t
t
3, 4
3, 4
SYSCLK
SYSCLK
SYSCLK to ARTRY high impedance
after precharge
Notes:
1. All output specifications are measured from the VM of the rising edge of SYSCLK to the output signal level defined in Figure 3-5 on
page 18. Both input and output timings are measured at the pin. Timings are determined by design.
2. This minimum parameter assumes CL = 0pF.
3. t
is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied
SYSCLK
by the period of SYSCLK to compute the actual time duration of the parameter in question.
4. Nominal precharge width for ARTRY is 1.0 t
.
SYSCLK
5. Guaranteed by design and characterization, and not tested.
6. Output Valid timing increases as the V in reduced. These values assumes V minimum of 1.35V.
DD
DD
7. See Alternate I/O Timing For 3.3V Bus on page 19
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
3. Electrical and Thermal Characteristics
Page 17 of 63
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