DD 2.X
Preliminary
PowerPC 750FX RISC Microprocessor
3.2 Clock AC Specifications
Table 3-6 provides the clock AC timing specifications as defined in Figure 3-1.
Table 3-6. Clock AC Timing Specifications (See Table 3-2 on page 10 for recommended operating
1,6
conditions
)
Value
Num
Characteristic
Unit
Notes
(Timing Reference)
Min.
400
20
Max.
800
200
50
Processor frequency
SYSCLK frequency
SYSCLK cycle time
MHz
MHz
ns
7
1, 6
1
2, 3
4
5.0
1.0
25
SYSCLK rise and fall slew rate
—
V/ns
%
3
3
SYSCLK duty cycle measured at 0.8V
Measurement Reference Voltage for SYSCLK (all I/O voltages)
SYSCLK cycle-to-cycle jitter
75
VM
0.65
V
SYSCLK
–
–
±150
ps
4, 3
5
Internal PLL relock time
100
µs
Notes:
1. Caution: The SYSCLK frequency and the PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)
frequency, CPU (core) frequency, and PLL frequency do not exceed their respective maximum or minimum operating frequencies.
Refer to the PLL_CFG[0:4] signal description in Table 5-2, “750FX Microprocessor PLL Configuration” on page 33 for valid
PLL_CFG[0:4] settings.
2. The SYSCLK slew rate applies between 0.4V and 1.0V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. See Section 3.3 Spread Spectrum Clock Generator (SSCG) on page 14 for long term jitter.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum amount of time
required for PLL lock after a stable V and SYSCLK are reached during the power-on reset sequence. This specification also
DD
applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held
asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
6. This is a statement of the capability of the 750FX I/O circuitry. Not all systems can run at the maximum SYSCLK frequency. Con-
tact IBM PowerPC Application Engineering for more information on high-speed bus design.
7. Lower voltage/frequency operation: For additional information, see 750FX Datasheet Supplement for DD2.X Revisions.
Figure 3-1. SYSCLK Input Timing Diagram
1
2
3
4
4
CVIH
VM
SYSCLK
CVIL
- Midpoint Voltage for SYSCLK
VM
SYSCLK
Body_750FX_DS_DD2.X.fm.2.0
June 9, 2003
3. Electrical and Thermal Characteristics
Page 13 of 63
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