Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
PPC405GPr New Mode Strapping Pin Assignments (Part 1 of 3)
Function
Option
Ball Strapping
AF2 AD16
(UART0_DTR) (UART0_RTS)
PLL Tuning
AF3
(UART0_Tx)
See the PowerPC 405GPr
Embedded Processor User’s
Manual for details.
Choice 1; TUNE[9:0] = 1010111100
Choice 2; TUNE[9:0] = 0100111000
Choice 3; TUNE[9:0] = 0100110110
Choice 4; TUNE[9:0] = 0100111100
Choice 5; TUNE[9:0] = 0100111000
Choice 6; TUNE[9:0] = 1000111100
Choice 7; TUNE[9:0] = 1000111110
Choice 8; TUNE[9:0] = 1011111110
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
D16
(DMAAck0)
B15
(DMAAck1)
AC9
GPIO5[TS3]
PLL Forward Divider A
Divide by 8
Divide by 7
Divide by 6
Divide by 5
Divide by 4
Divide by 3
Divide by 2
Divide by 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
P25
(EMCTxD3)
L24
(EMCTxD2)
AE8
GPIO6[TS4]
PLL Forward Divider B
Divide by 8
Divide by 7
Divide by 6
Divide by 5
Divide by 4
Divide by 3
Divide by 2
Divide by 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
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