Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
PPC405GPr Legacy Mode Strapping Pin Assignments (Part 2 of 2)
Function
Option
Ball Strapping
2
L25
(EMCTxD1)
J26
(EMCTxD0)
OPB Divider from PLB
Divide by 1
Divide by 2
Divide by 3
Divide by 4
0
0
0
1
1
0
1
1
2, 3
D18
C20
PCI Divider from PLB
(GPIO1[TS1E]) (GPIO2[TS2E])
Divide by 1
Divide by 2
Divide by 3
Divide by 4
0
0
1
1
0
1
0
1
2
K25
(EMCTxErr)
K23
(EMCTxEn)
External Bus Divider from PLB
Divide by 2
Divide by 3
Divide by 4
Divide by 5
0
0
1
1
0
1
0
1
ROM Width
AD2
(UART1_RTS/
UART1_DTR)
AC2
(UART1_Tx)
8-bit ROM
16-bit ROM
32-bit ROM
Reserved
0
0
1
1
0
1
0
1
ROM Location
U2
(HoldAck)
PPC405GPr Peripheral Attach
PPC405GPr PCI Attach
0
1
PCI Asynchronous Mode Enable
Y3
(ExtAck)
Synchronous PCI Mode
Asynchronous Mode
0
1
3
AF18
(GPIO4[TS2O])
PCI Arbiter Enable
Internal Arbiter Disabled
Internal Arbiter Enabled
0
1
Note:
1. The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the
PPC405GPr. These bits are shown for information only; and do not require modification except in special clocking circumstances
such as spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405GPr,
visit the technical documents area of the IBM PowerPC web site.
2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in “Clocking
Specifications” on page 60. Further requirements are detailed in the Clocking chapter of the PowerPC 405GPr Embedded
Processor User’s Manual.
3. Additional consideration must be given to pins that normally function as Trace signals. Improved design margin can be gained by
using tri-state buffers instead of strapping resistors, and minimizing trace lengths and stubs.
52
IBM [ IBM ]
