Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signal Functional Description (Part 2 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 45 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 45 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 46.
Signal
Name
Description
I/OType
Notes
5V tolerant
3.3V PCI
PCIReq1:5
Used as PCIReq1:5 input when internal arbiter is used.
I
Gnt0 when internal arbiter is used
or
5V tolerant
3.3V PCI
PCIGnt0[Req]
O
O
Req when external arbiter is used.
5V tolerant
3.3V PCI
PCIGnt1:5
Ethernet Interface
PHYRxD3:0
Used as PCIGnt1:5 output when internal arbiter is used.
Received data. This is a nibble wide bus from the PHY. The data
is synchronous with the PHYRxClk.
5V tolerant
3.3V LVTTL
I
O
I
1
6
1
1
Transmit data. A nibble wide data bus towards the net. The data
is synchronous to the PHYTxClk.
5V tolerant
3.3V LVTTL
EMCTxD3:0
PHYRxErr
PHYRxClk
Receive Error. This signal comes from the PHY and is
synchronous to the PHYRxClk.
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
Receiver Medium clock. This signal is generated by the PHY.
I
Receive Data Valid. Data on the Data Bus is valid when this
signal is activated. Deassertion of this signal indicates end of the
frame reception.
5V tolerant
3.3V LVTTL
PHYRxDV
PHYCrS
I
I
1
1
6
Carrier Sense signal from the PHY. This is an asynchronous
signal.
5V tolerant
3.3V LVTTL
Transmit Error. This signal is generated by the Ethernet
controller, is connected to the PHY and is synchronous with the
PHYTxClk. It informs the PHY that an error was detected.
5V tolerant
3.3V LVTTL
EMCTxErr
O
Transmit Enable. This signal is driven by the EMAC to the PHY.
Data is valid during the active state of this signal. Deassertion of
this signal indicates end of frame transmission. This signal is
synchronous to the PHYTxClk.
5V tolerant
3.3V LVTTL
EMCTxEn
O
6
This clock comes from the PHY and is the Medium Transmit
clock.
5V tolerant
3.3V LVTTL
PHYTxClk
PHYCol
I
I
1
1
5V tolerant
3.3V LVTTL
Collision signal from the PHY. This is an asynchronous signal.
Management Data Clock. The MDClk is sourced to the PHY. This
clock has a period of 400ns, adjustable via
EMAC0_STACR[OPBC]. Management information is transferred
synchronously with respect to this clock.
5V tolerant
3.3V LVTTL
EMCMDClk
O
Management Data Input/Output is a bidirectional signal between
EMCMDIO[PHYMDIO] the Ethernet controller and the PHY. It is used to transfer control
and status information.
5V tolerant
3.3V LVTTL
I/O
1
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