Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
I/O Specifications—Group 1 (Part 2 of 3)
Notes:
1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz
and 2ns for 33.33MHz.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at
2.4 V and I/O L is specified at 0.4 V.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
I/O H
(min)
I/O L
(min)
(T min)
(T min)
(T max)
(T min)
IS
IH
OV
OH
Internal Peripheral Interface
IICSCL
na
na
na
na
na
na
na
na
na
na
na
na
na
na
15.3
15.3
10.3
10.3
10.3
10.3
10.3
10.3
10.3
10.3
10.2
10.2
7.1
7.1
7.1
7.1
7.1
7.1
7.1
7.1
IICSDA
UART0_CTS
UART0_DCD
UART0_DSR
UART0_DTR
UART0_RI
na
na
na
na
UART0_RTS
UART0_Rx
UART0_Tx
UART1_RTS/
UART1_DTR
UART1_DSR/
UART1_CTS
UART1_Rx
UART1_Tx
UARTSerClk
na
na
na
na
na
na
10.3
na
7.1
na
na
na
na
na
na
10.3
na
na
7.1
na
na
na
na
na
Interrupts Interface
IRQ0:6[GPIO17:23]
10.3
7.1
JTAG Interface
TCK
TDI
na
na
na
na
7.1
na
na
async
async
async
async
async
TDO
TMS
TRST
10.3
na
na
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