Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Signal Functional Description (Part 7 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 29.
Signal
AGND
Name
Clean Ground input for the PLL.
Description
I/OType
Notes
I
5V tolerant
3.3V LVTTL
SysErr
Halt
Set to 1 when a Machine Check is generated.
Halt from external debugger.
O
5V tolerant
3.3V LVTTL
I
1, 2
1, 6
General Purpose I/O
or
GPIO1[TS1E]
GPIO2[TS2E]
5V tolerant
3.3V LVTTL
I/O[O]
Even Trace execution status. To access this function, software
must toggle a DCR bit.
General Purpose I/O
or
5V tolerant
3.3V LVTTL
GPIO3[TS1O]
GPIO4[TS2O]
GPIO5:8[TS3:6]
I/O[O]
I/O[O]
I/O[O]
1, 6
1, 6
1, 6
Odd Trace execution status. To access this function, software
must toggle a DCR bit.
General Purpose I/O
or
5V tolerant
3.3V LVTTL
Odd Trace execution status. To access this function, software
must toggle a DCR bit.
General Purpose I/O
or
5V tolerant
3.3V LVTTL
Trace status. To access this function, software must toggle a
DCR bit.
General Purpose I/O
or
Trace interface clock. A toggling signal that is always half of the
CPU core frequency. To access this function, software must
toggle a DCR bit.
5V tolerant
3.3V LVTTL
GPIO9[TrcClk]
I/O[O]
1, 6
1, 6
Note: Initialization strapping must hold this pin low (0) during
reset.
General Purpose I/O.
3.3V LVTTL
w/pull-down
Note: The pull-up initialization strapping resistor must be 1kΩ
rather than 3kΩ in order to overcome the internal pull-down
resistor.
GPIO24
TestEn
I/O
Test Enable. Used only for manufacturing tests. Pull down for
normal operation.
1.8V CMOS
w/pull-down
I
I
An external clock input that can be used to clock the timers in the
CPU core.
5V tolerant
3.3V LVTTL
TmrClk
1
Trace Interface
Even Trace execution status. To access this function, software
must toggle a DCR bit
[TS1E]GPIO1
[TS2E]GPIO2
5V tolerant
3.3V LVTTL
O[I/O]
1, 6
or
General Purpose I/O.
36
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