PowerPC 405GP Embedded Processor Data Sheet
PPC405GP Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
Clock
Control
Reset
OCM
SRAM
Power
Mgmt
DCRs
Timers
MMU
DOCM
IOCM
OCM
Control
PPC405
Processor Core
GPIO
IIC
UART
UART
DCR Bus
Trace
ICU
JTAG
DCU
16KB
I-Cache
8KB
D-Cache
On-chip Peripheral Bus (OPB)
OPB
Arb
DMA
Controller
(4-Channel)
MAL
Ethernet
Bridge
Arb
Processor Local Bus (PLB)
Code
Decompression
(CodePack)
External
Bus
Controller
External
SDRAM
Controller
Bus Master
PCI Bridge
Controller
66 MHz max (async)
33 MHz max (sync)
MII
13-bit addr
32-bit data
32-bit addr
32-bit data
The PPC405GP is designed using the IBM Microelectronics Blue LogicTM methodology in which major
functional blocks are integrated together to create an application-specific ASIC product. This approach
provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture.
Page 5 of 60
6/20/03
IBM [ IBM ]
