PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description (Part 7 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 33 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 33 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 33.
Signal Name
Description
I/O
Type
Notes
5V tolerant
3.3V LVTTL
SysErr
Set to 1 when a Machine Check is generated.
O
5V tolerant
3.3V LVTTL
Halt
Halt from external debugger.
I
1, 2
1, 6
General Purpose I/O
or
GPIO1[TS1E]
GPIO2[TS2E]
5V tolerant
3.3V LVTTL
I/O[O]
Even Trace execution status. To access this function, software
must toggle a DCR bit.
General Purpose I/O
or
5V tolerant
3.3V LVTTL
GPIO3[TS1O]
GPIO4[TS2O]
GPIO5:8[TS3:6]
I/O[O]
I/O[O]
I/O[O]
1
1, 6
1
Odd Trace execution status. To access this function, software
must toggle a DCR bit.
General Purpose I/O
or
5V tolerant
3.3V LVTTL
Odd Trace execution status. To access this function, software
must toggle a DCR bit.
General Purpose I/O
or
5V tolerant
3.3V LVTTL
Trace status. To access this function, software must toggle a
DCR bit.
General Purpose I/O
or
5V tolerant
3.3V LVTTL
GPIO9[TrcClk]
I/O[O]
1
Trace interface clock. A toggling signal that is always half of the
CPU core frequency. To access this function, software must
toggle a DCR bit.
Test Enable. Used only for manufacturing tests. Pull down for
normal operation.
2.5V CMOS
w/pull-down
TestEn
RcvrInh
I
I
I
I
Receiver Inhibit. Used only for manufacturing tests. Pull up for
normal operation.
5V tolerant
3.3V LVTTL
2
2
1
Driver Inhibit 1 and 2. Used only for manufacturing tests. Pull up
for normal operation.
5V tolerant
3.3V LVTTL
DrvrInh1:2
An external clock input that can be used to clock the timers in the
CPU core.
5V tolerant
3.3V LVTTL
TmrClk
Trace Interface
Even Trace execution status. To access this function, software
must toggle a DCR bit
[TS1E]GPIO1
[TS2E]GPIO2
5V tolerant
3.3V LVTTL
O[I/O]
1, 6
or
General Purpose I/O.
Page 40 of 60
6/20/03
IBM [ IBM ]
