Preliminary
PowerPC 405EP Embedded Processor Data Sheet
Notes: 1. In the following I/O Specifications tables a timing value of na means “not applicable” and dc means
“don’t care.”
2. See “Test Conditions” on page 42 for output capacitive loading.
I/O Specifications—Group 1 (Part 1 of 2)
Notes:
1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz
and 2ns for 33.33MHz.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise
filter selected. See the CPC0_EPCTL register PowerPC 405EP Embedded Processor User’s Manual.
3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at
2.4 V and I/O L is specified at 0.4 V.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
I/O H
(min)
I/O L
(min)
(T min)
(T min)
(T max)
(T min)
IS
IH
OV
OH
PCI Interface
PCIAD31:00
PCIC3:0/BE3:0
PCIClk
3
3
0
0
6
6
1
1
0.5
0.5
na
1.5
1.5
na
PCIClk
PCIClk
async
1
1
na
3
na
0
na
6
na
1
PCIDevSel
PCIFrame
0.5
0.5
1.5
1.5
PCIClk
PCIClk
1
1
3
0
6
1
PCIGnt0/Req
PCIGnt1:2
na
na
6
1
0.5
1.5
PCIClk
1
PCIIDSel
3
na
3
0
na
0
na
na
6
na
na
1
na
0.5
0.5
0.5
0.5
na
1.5
1.5
1.5
1.5
PCIClk
PCIClk
PCIClk
PCIClk
PCIClk
1
1
1
1
1
PCIINT[PerWE]
PCIIRDY
PCIParity
PCIPErr
3
0
6
1
3
0
6
1
PCIReq0/Gnt
PCIReq1:2
5
0
na
na
na
na
PCIClk
1
PCIReset
na
na
3
na
na
0
na
na
6
na
na
1
0.5
0.5
0.5
0.5
1.5
1.5
1.5
1.5
PCIClk
PCIClk
PCIClk
PCIClk
1
1
1
1
PCISErr
PCIStop
PCITRDY
3
0
6
1
Ethernet Interface
EMC0MDClk
na
na
0
settable
2
10.3
10.3
7.1
7.1
async
2
2
1 OPB clock 1 OPB clock
period + 10ns
EMC0MDIO
100
EMC0MDClk
period
EMC0Tx0:1D3:0
EMC0Tx0:1En
EMC0Tx0:1Err
PHY0Col0:1
na
na
na
2
na
na
na
3
14
14
14
na
na
na
na
na
na
na
5
10.3
10.3
10.3
na
7.1
7.1
7.1
na
na
na
na
na
na
na
PHY0TxClk
PHY0TxClk
PHY0TxClk
PHY0RxClk
PHY0RxClk
async
2
2
2
2
2
2
2
2
2
2
5
5
na
na
na
na
na
na
na
PHY0CrS0:1
2
3
na
PHY0Rx0:1Clk
PHY0Rx0:1D3:0
PHY0Rx0:1DV
PHY0Rx0:1Err
PHY0Tx0:1Clk
na
2
na
4
na
na
PHY0RxClk
PHY0RxClk
PHY0RxClk
async
2
4
na
2
4
na
na
na
na
Page 47 of 52
6/9/03
IBM [ IBM ]
