PowerPC 405CR Embedded Processor Data Sheet
General Purpose IO (GPIO) Controller
• Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus
master accesses.
• All GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO
capabilities acts as a GPIO or is used for another purpose. The 23 GPIOs are multiplexed with:
- 7 of 8 chip selects.
- All seven external interrupts.
- All nine instruction trace pins.
• Each GPIO output is separately programmable to emulate an open-drain driver (two states, drive to zero
or open circuit).
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between
the various sources of interrupts and the local PowerPC processor.
Features include:
• Supports 7 external and 10 internal interrupts
• Edge triggered or level-sensitive
• Positive or negative active
• Non-critical or critical interrupt to PPC405 processor core
• Programmable critical interrupt priority ordering
• Programmable critical interrupt vector for faster vector processing
JTAG
• IEEE 1149.1 test access port
• IBM RISCWatch debugger support
• JTAG Boundary Scan Description Language (BSDL)
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6/18/03
IBM [ IBM ]
