PowerPC 405CR Embedded Processor Data Sheet
Signals Listed Alphabetically (Part 3 of 7)
Signal Name
Ball
Interface Group
Page
T5
T10
T11
T16
U4
U17
V3
GND (cont)
V18
W2
W19
Y1
Power
28
Y6
Y11
Y15
Y20
GPIO1[TS1E]
GPIO2[TS2E]
GPIO3[TS1O]
GPIO4[TS2O]
GPIO5[TS3]
GPIO6[TS4]
GPIO7[TS5]
GPIO8[TS6]
GPIO9[TrcClk]
B18
D16
C17
P18
T17
W18
Y19
W13
V6
System
27
Halt
E19
System
27
25
HoldAck
HoldPri
T4
T3
V2
External Master Peripheral
Internal Peripheral
HoldReq
IICSCL
IICSDA
U15
25
25
W17 Internal Peripheral
IRQ0[GPIO17]
IRQ1[GPIO18]
IRQ2[GPIO19]
IRQ3[GPIO20]
IRQ4[GPIO21]
IRQ5[GPIO22]
IRQ6[GPIO23]
D18
C20
E18
D20
G17
F18
Interrupts
26
W20
MemAddr0
MemAddr1
MemAddr2
MemAddr3
MemAddr4
MemAddr5
MemAddr6
MemAddr7
MemAddr8
MemAddr9
MemAddr10
MemAddr11
MemAddr12
Y7
W7
V8
U7
Y4
U6
W4
V5
W3
V4
U3
V1
T2
SDRAM
23
Note: During a CAS cycle MemAddr0 is the least significant bit (lsb) on
this bus.
13
6/18/03
IBM [ IBM ]
