PowerPC 405CR Embedded Controller Data Sheet
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable default initial
conditions prior to PPC405CR start-up. The actual capture instant is the nearest reference clock edge before
the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down
(logical 0) resistors to select the desired default conditions. These pins are use for strap functions only during
reset. They are used for other signals during normal operation. The following table lists the strapping pins
along with their functions and strapping options:
Strapping Pin Assignments
Function
Option
Ball Strapping
PLL Tuning
W15
0
U13
0
V20
0
for 6 ≤ M ≤ 7 use choice 3
for 7 < M ≤ 12 use choice 5
for 12 < M ≤ 32 use choice 6
See Note.
Choice 1; TUNE[5:0] = 010001
Choice 2; TUNE[5:0] = 010010
Choice 3; TUNE[5:0] = 010011
Choice 4; TUNE[5:0] = 010100
Choice 5; TUNE[5:0] = 010101
Choice 6; TUNE[5:0] = 010110
Choice 7; TUNE[5:0] = 010111
Choice 8; TUNE[5:0] = 100100
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
PLL Forward Divider
C16
0
B17
0
Bypass mode
Divide by 3
Divide by 4
Divide by 6
0
1
1
0
1
1
PLL Feedback Divider
PLB Divider from CPU
OPB Divider from PLB
External Bus Divider from PLB
B16
0
A14
0
Divide by 1
Divide by 2
Divide by 3
Divide by 4
0
1
1
0
1
1
B18
0
D16
0
Divide by 1
Divide by 2
Divide by 3
Divide by 4
0
1
1
0
1
1
T4
0
U5
0
Divide by 1
Divide by 2
Divide by 3
Divide by 4
0
1
1
0
1
1
C17
0
P18
0
Divide by 2
Divide by 3
Divide by 4
Divide by 5
0
1
1
0
1
1
39
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