PowerPC 405CR Embedded Controller Data Sheet
Test Conditions
Output
Pin
Clock timing and switching characteristics are specified in accordance
with operating conditions shown in the table “Recommended DC
Operating Conditions.” AC specifications are characterized at
C
L
C = 50pf for all signals
L
V
= 3.14V and T = 100˚C with the 50pF test load (C ) shown in
DD
J
L
the figure at right.
SysClk and MemClk Timing
Symbol
Parameter
Min
Max
Units
SysClk Input
F
SysClk clock input frequency
SysClk clock period
25
15
–
66.6
40
MHz
ns
C
T
C
T
Clock edge stability
0.15
ns
CS
T
Clock input high time
Clock input low time
40% of nominal period 60% of nominal period
40% of nominal period 60% of nominal period
ns
CH
T
ns
CL
Note: Input slew rate > 2V/ns
MemClk Output
F
T
F
T
MemClk clock output frequency—200MHz
MemClk clock period—200MHz
MemClk clock output frequency—266MHz
MemClk clock period—266MHz
Clock output high time
100
MHz
ns
C
C
C
C
10
133
MHz
ns
7.5
T
35% of nominal period 65% of nominal period
35% of nominal period 65% of nominal period
ns
CH
T
Clock output low time
ns
CL
Timing Waveform
2.0V
1.5V
0.8V
T
T
CL
CH
T
C
32
IBM [ IBM ]
