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IBM25EMPPC750LCBE4000 参数 Datasheet PDF下载

IBM25EMPPC750LCBE4000图片预览
型号: IBM25EMPPC750LCBE4000
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 400MHz, CMOS, CBGA360, 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360]
分类和应用: 时钟外围集成电路
文件页数/大小: 50 页 / 600 K
品牌: IBM [ IBM ]
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PowerPC 740 and PowerPC 750 Embedded Microprocessor  
IBM CMOS 0.20 um Copper Technology EMPPC740L and EMPPC750L  
• Floating-point unit  
- Support for IEEE-754 standard single- and double-precision floating-point arithmetic.  
- 3 cycle latency, 1 cycle throughput, single-precision multiply-add.  
- 3 cycle latency, 1 cycle throughput, double-precision add.  
- 4 cycle latency, 2 cycle throughput, double-precision multiply-add.  
- Hardware support for divide.  
- Hardware support for denormalized numbers.  
- Time deterministic non-IEEE mode.  
• System unit  
- Executes CR logical instructions and miscellaneous system instructions.  
- Special register transfer instructions.  
• Cache structure  
- 32K, 32-byte line, 8-way set associative instruction cache.  
- 32K, 32-byte line, 8-way set associative data cache.  
- Single-cycle cache access.  
- Pseudo-LRU replacement.  
- Copy-back or write-through data cache (on a page per page basis).  
- Supports all PowerPC memory coherency modes.  
- Non-blocking instruction and data cache (one outstanding miss under hits).  
- No snooping of instruction cache.  
• Memory management unit  
- 128 entry, 2-way set associative instruction TLB.  
- 128 entry, 2-way set associative data TLB.  
- Hardware reload for TLB's.  
- 4 instruction BAT's and 4 data BATs.  
52  
- Virtual memory support for up to 4 exabytes (2 ) virtual memory.  
32  
- Real memory support for up to 4 gigabytes (2 ) of physical memory.  
• Level 2 (L2) cache interface (Not available on the 740)  
- Internal L2 cache controller and 4K-entry tags; external data SRAMs.  
- 256K, 512K, and 1 Mbyte 2-way set associative L2 cache support.  
- Copy-back or write-through data cache (on a page basis, or for all L2).  
- 64-byte (256K/512K) and 128-byte (l-Mbyte) sectored line size.  
- Supports flow-through (reg-buf) synchronous burst SRAMs, pipelined (reg-reg) synchronous burst  
SRAMs, and pipelined (reg-reg) late-write synchronous burst SRAMs.  
- Design supports Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, and ÷3; however, this specifica-  
tion supports the L2 frequency range specified in Section “L2 Clock AC Specifications,on page 16.  
For higher L2 frequencies not supported in this document, please contact your IBM marketing repre-  
sentative.  
Page 4  
Version 1.51  
PowerPC 740 and PowerPC 750 Datasheet  
5/20/99  
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