tigh tly regu lated sou rce of power. Th erefore, it is stron gly recom m en ded th at th e sys-
tem design er place at least on e decou plin g capacitor with a low ESR (effective series
resistan ce) ratin g at each Vdd an d OVdd pin (an d L2OVdd for th e 360 CBGA) of th e
PPC740 an d PPC750. It is also recom m en ded th at th ese decou plin g capacitors receive
th eir power from separate Vdd, OVdd an d GND power plan es in th e PCB, u tilizin g sh ort
traces to m in im ize in du ctan ce.
Th ese capacitors sh ou ld ran ge in valu e from 220 pF to 10 µF to provide both h igh - an d
low- frequ en cy filterin g, an d sh ou ld be placed as close as possible to th eir associated
Vdd or OVdd pin s. Su ggested valu es for th e Vdd pin s -- 220 pF (ceram ic), 0.01 µF
(ceram ic), an d 0.1 µf (ceram ic). Su ggested valu es for th e OVdd pin s -- 0.01 µF
(ceram ic), 0.1 µf (ceram ic), an d 10 µF (tan talu m ). On ly SMT (su rface-m ou n t tech n ology)
capacitors sh ou ld be u sed to m in im ize lead in du ctan ce.
In addition , it is recom m en ded th at th ere be several bu lk storage capacitors distribu ted
arou n d th e PCB, feedin g th e Vdd an d OVdd plan es, to en able qu ick rech argin g of th e
sm aller ch ip capacitors. Th ese bu lk capacitors sh ou ld h ave a low ESR (equ ivalen t
series resistan ce) ratin g to en su re th e qu ick respon se tim e n ecessary. Th ey sh ou ld also
be con n ected to th e power an d grou n d plan es th rou gh two vias to m in im ize in du ctan ce.
Su ggested bu lk capacitors -- 100 µF (AVX TPS tan talu m ) or 330 µF (AVX TPS tan ta-
lu m ).
8.4 Connection Recommendations
To en su re reliable operation , it is h igh ly recom m en ded to con n ect u n u sed in pu ts to an
appropriate sign al level. Un u sed active low in pu ts sh ou ld be tied to Vdd. Un u sed active
h igh in pu ts sh ou ld be con n ected to GND. All NC (n o-con n ect) sign als m u st rem ain
u n con n ected.
Power an d grou n d con n ection s m u st be m ade to all extern al Vdd, OVdd, an d GND,
pin s of th e PPC740 an d PPC750.
Extern al clock rou tin g sh ou ld en su re th at th e risin g-edge of th e L2 clock is coin ciden t
at th e CLK in pu t of all SRAMs an d at th e L2SYNC_IN in pu t of th e PPC740 an d PPC750.
Th e L2CLKOUTA n etwork cou ld be u sed on ly, or th e L2CLKOUTB n etwork cou ld also
be u sed depen din g on th e loadin g, frequ en cy, an d n u m ber of SRAMs.
8.5 Output Buffer DC Impedance
Th e PPC750 60x an d L2 I/ O drivers were ch aracterized over process, voltage an d tem -
peratu re. To m easu re Z , an extern al resistor is con n ected to th e ch ip pad, eith er to
0
OVdd or GND. Th en , th e valu e of su ch resistor is varied u n til th e pad voltage is OVdd/
2; see Section Figu re 18., "Driver Im pedan ce Measu rem en t".
Th e ou tpu t im pedan ce is actu ally th e average of two com pon en ts, th e resistan ces of th e
pu ll-u p an d pu ll-down devices. Wh en Data is h eld low, SW1 is closed (SW2 is open ),
an d R is trim m ed u n til Pad = OVdd/ 2. R th en becom es th e resistan ce of th e pu ll-
N
N
down devices. Wh en Data is h eld h igh , SW2 is closed (SW1 is open ), an d R is trim m ed
P
u n til Pad = OVdd/ 2. R th en becom es th e resistan ce of th e pu ll-u p devices. With a
P
properly design ed driver R an d R are close to each oth er in valu e. Th en Z = (R +
P
N
0
P
R )/ 2.
N
PPC740 and PPC750 Hardware Specifications
34 of 44
Preliminary and subject to change without notice
IBM [ IBM ]
