8.0 System Design Information
This section provides electrical and thermal design recommendations for successful
application of the PPC740 and PPC 750.
8.1 PLL Configuration
The PLL for the PPC740 and PPC750 is configured by the PLL_CFG[0-3-] signals. For a
given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and
VCO frequency of operation. The PLL configuration for the PPC740 and PPC750 is
shown in Table 16 for nominal frequencies.
Table 16. PPC740 and PPC750 Microprocessor PLL Configuration
Processor
to Bus
Frequency
Ratio
(r)
Rsv
1
7.5x
7x
PLL
Bypass
3
Rsv
1
6.5x
Rsv
1
4.5x
3x
5.5x
4x
5x
8x
6x
3.5x
Off
4
Frequency Range Supported by VCO having an example
range of VCO
min
=300 to VCO
max
=533 (MHz)
VCO
Divider
(d)
n/a
2
2
n/a
n/a
2
n/a
2
2
2
2
2
2
2
2
n/a
SYSCLK
Min=
VCO
min
/(r*d)
n/a
25
2
25
2
n/a
n/a
25
2
n/a
33
50
27
37
30
25
2
25
43
n/a
Max=
VCO
max
/(r*d)
n/a
35
38
n/a
n/a
41
n/a
59
83
5
48
67
150
1011
1100
1101
1110
1111
11
12
13
14
15
53
33
44
83
5
n/a
Off
Off
266
n/a
n/a
n/a
150
n/a
266
Core
Min=
VCO
min
/d
n/a
150
Max=
VCO
max
/d
n/a
266
PLL_CFG
(0:3)
bin
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
dec
0
1
2
3
4
5
6
7
8
9
10
Notes:
1. Reserved settings.
2. SYSCLK min is limited by the lowest frequency that manufacturing will support, see Section 3.1.2.1,
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is dis-
PPC740 and PPC750 Hardware Specifications
32 of 44
Preliminary and subject to change without notice
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