Datasheet
CPC945 Bridge and Memory Controller
Preliminary
Table 4-11. Clock and PLL Signal Pins
I/O
Supply
Voltage
Signal
Type
Signal
Levels
Signal Name
Signal Description
Analog
GND
PI_REFCLK_AGND
PI_REFCLK_AVDD
Analog ground for PLL
Analog power for PLL
Analog
Power
1.5 V
1.5 V
PI_REFCLK_P
PI_REFCLK_N
Differential processor interface reference clock positive input.
This is a 1.3 V -1.5 V signal.
Input
Input
1.3 V-1.5 V
2.5 V
VDD2
VDD5
HT_REFCLK_P
HT_REFCLK_N
HyperTransport clock reference input. This is a 2.5 V signal.
Analog ground for PLL
Analog
GND
HT_REFCLK_AGND
HT_REFCLK_AVDD
HT_REFCLK_AVDD2
Analog
Power
Analog power for PLL
1.65 V- 2.75 V
2.5 V
DDR_REFCLK_P
DDR_REFCLK_N
DDR2 reference clock input
Input
VDD5
Analog
GND
DDR_REFCLK_AGND Analog ground for PLL
DDR_REFCLK_AVDD Analog power for PLL
Analog
Power
1.5 V
1.5 V
1.5 V
VDD
PCIE_REFCLK_P
PCIE_REFCLK_N
Reference clock input for the PCI Express PLL.
This is a 1.5 V signal.
Input
PCIE_REFCLK_AGNDA
PCIE_REFCLK_AGNDB
Analog
GND
Analog ground for PLL
PCIE_REFCLK_AVDD2
PCIE_REFCLK_AVDDA Analog power for PLL
PCIE_REFCLK_AVDDB
Analog
Power
1.65 V-2.75 V
PMR_CLK_P
PMR_CLK_N
Reference clock input for power management
External clock stop for power management
Input
Input
2.5 V
2.5 V
VDD5
VDD5
PMR_CLK_STOP
Note: AVDDx supplies must have dedicated filters; otherwise, severe degradation can occur when AVDDx supplies are shared
between PLLs.
Table 4-12. JTAG and Test Support Signal Pins (Page 1 of 2)
I/O
Supply
Voltage
Signal
Type
Signal
Levels
Signal Name
Signal Description
CE1_DI1_TMS
CE1_DI2_TRST
CE1_LT_TCK
CE0_TEST
JTAG TMS. It should be tied high during normal (nontest) operation.
JTAG TRST. It should be tied high during normal (nontest) operation
JTAG TCK. It should be tied high during normal (nontest) operation.
IBM test pin. Set this test pin to ‘0’ for normal (nontest) operation.
JTAG
JTAG
JTAG
Test
2.5 V
2.5 V
2.5 V
1.5 V
VDD5
VDD5
VDD5
VDD
Dimensions and Pin Information
Page 42 of 69
A15-6009-03
December 18, 2007 - IBM Confidential
IBM [ IBM ]
