Datasheet
CPC945 Bridge and Memory Controller
Preliminary
Table 3-4. Recommended Functional dc Operating Ratings (Page 2 of 2)
Parameter
2.5 V input logic low
Symbol
VILH2
Minimum
0
Typical
Maximum
0.7
Units
V
Notes
VDD2 input logic high
DD2 input logic low
VIH1
VIL1
1.6
V
V
4
4
0.65 × VDD2
0
V
0.35 × VDD2
2.5 V output high
2.5 V output low
VOH2
VOL2
2
0
2.7
0.4
V
V
VDD2 output logic high
VDD2 0utput logic low
VOH1
VOL1
1.6
V
V
4
4
0.75 × VDD2
0
0.25 × VDD2
Input leakage current
Ambient temperature (startup condition)
Die junction temperature
Notes:
IL
0
0
0
<1
—
—
10
70
90
μA
°C
°C
TA
TJ
1. The PLL analog power supply and ground pins must be filtered with a inductive-capacitive (LC) filter. See Figure 3-1, Analog VDD
Filtering for the HyperTransport and PCI Express Phase-Locked Loops, on page 24 for details.
2. At 533 MHz core frequency, 533 MTps DDR2, 1250 MTps processor interface, nominal supply voltages, and 70°C junction temper-
ature. Configurations with lower speeds and narrower interfaces (333 MTps 64-bit DDR2, 600 MTps processor interface, 400
MTps 8-bit HyperTransport) will consume less power. Contact IBM applications engineering for more details.
3. The four PLLs consume current from both the VDD and VPLL AVDD, AVDD2, AVDDA, AVDDB supplies. These currents are small
relative to the total core current.
4. Processor interface supply voltage VDD2 can vary from 1.3 V to 1.5 V, depending on system or card design requirements and pro-
cessor I/O voltage specifications. Perform necessary simulations or provide a variable voltage and determine, experimentally,
which voltage best meets their requirements. This voltage must be the same for both processor (OVDD) and bridge (VDD2).
5. The core voltage must be brought up first, followed by the I/O voltages. Note that correct I2C slave interface operation depends on
stable core, processor I/O, and DDR I/O voltages. No voltage should be applied to an I/O pad if the associated power supply is not
turned on.
Figure 3-1. Analog V Filtering for the HyperTransport and PCI Express Phase-Locked Loops
DD
Ferrite Bead
Supply
AVDDx
1.0 μF ceramic
Murata BLM15AG102SN1
System Board GND
Figure 3-2. Analog V Filtering for the Processor Interface and DDR2 Interface Phase-Locked Loops
DD
Ferrite Bead
Supply
AVDDx
0.1 μF ceramic
BLM31AF700SN1
System Board GND
Electrical and Thermal Characteristics
Page 24 of 69
A15-6009-03
December 18, 2007 - IBM Confidential
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