IBM13N64644HCA
IBM13N64734HCA
64M x 64/72 Two-Bank Unbuffered SDRAM Module
Preliminary
Clock and Clock Enable Parameters
-75A
Symbol
Parameter
Units
Notes
Min.
7.5
—
Max.
1000
5.4
—
t
Clock Cycle Time, CAS Latency = 3
Clock Access Time, CAS Latency = 3
Clock High Pulse Width
ns
ns
ns
ns
ns
ns
ns
ns
CK3
t
1
2
2
AC3
t
2.5
2.5
1.5
0.8
0
CKH
t
Clock Low Pulse Width
—
CKL
t
Clock Enable Set-up Time
—
CES
t
Clock Enable Hold Time
—
CEH
t
Power down mode Entry Time
Transition Time (Rise and Fall)
7.5
10
SB
t
0.5
T
1. Access time is measured at 1.4V. In AC Characteristics section, see notes.
2. t is the pulse width of CLK measured from the positive edge to the negative edge referenced to V (min). t is the pulse
CKL
CKH
IH
width of CLK measured from the negative edge to the positive edge referenced to V (max).
IL
Common Parameters
-75A
Symbol
Parameter
Units
Notes
Min.
1.5
0.8
1.5
0.8
20.0
67.5
45
Max.
—
t
Command Setup Time
Command Hold Time
ns
ns
CS
t
—
CH
t
Address and Bank Select Set-up Time
Address and Bank Select Hold Time
RAS to CAS Delay
—
ns
AS
t
—
ns
AH
t
1
1
1
1
1
—
ns
RCD
t
Bank Cycle Time
—
ns
RC
t
Active Command Period
Precharge Time
100000
—
ns
RAS
t
20.0
15
ns
RP
t
Bank to Bank Delay Time
CAS to CAS Delay Time
—
ns
RRD
t
1
—
CLK
CCD
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
09K3608.F38386
7/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 12 of 18
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