IBM13N16644JCA
IBM13N16734JCA
16M x 64/72 One-Bank Unbuffered SDRAM Module
Serial Presence Detect
(Part 1 of 2)
Byte #
0
1
2
3
4
5
6-7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36 - 61
62
1.
2.
3.
4.
5.
6.
7.
Description
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Banks
Data Width of Assembly
Voltage Interface Level of this Assembly
SDRAM Device Cycle Time at CL=3
SDRAM Device Access Time from Clock at CL=3
DIMM Configuration Type
Refresh Rate/Type
Primary SDRAM Device Width
Error Checking SDRAM Device Width
16M x 64
16M x 72
16M x 64
16 M x 72
16M x 64
16M x 72
SPD Entry Value
128
256
SDRAM
12
10
1
x64
x72
LVTTL
7.5ns
5.4ns
Non-Parity
ECC
SR/1x(15.625us)
x8
N/A
x8
1 Clock
1,2,4,8, Full Page
4
2, 3
0
0
Unbuffered
Wr-1/Rd Burst, Precharge All,
Auto-Precharge, V
DD
+/- 10%
15.0ns
9.0ns
N/A
N/A
20ns
15ns
20ns
45ns
128MB
1.5ns
0.8ns
1.5ns
0.8ns
Undefined
2
Serial PD Data Entry (Hexa-
decimal)
80
08
04
0C
0A
01
4000
4800
01
75
54
00
02
80
08
00
08
01
8F
04
06
01
01
00
0E
F0
90
00
00
14
0F
14
2D
20
15
08
15
08
00
02
Notes
SDRAM Device Attr: Min Clk Delay, Random Col Access
SDRAM Device Attributes: Burst Lengths Supported
SDRAM Device Attributes: Number of Device Banks
SDRAM Device Attributes: CAS Latencies Supported
SDRAM Device Attributes: CS Latency
SDRAM Device Attributes: WE Latency
SDRAM Module Attributes
SDRAM Device Attributes: General
Minimum Clock Cycle at CL=2
Maximum Data Access Time (t
AC
) from Clock at CL=2
Minimum Clock Cycle Time at CL=1
Maximum Data Access Time (t
AC
) from Clock at CL=1
Minimum Row Precharge Time (t
RP
)
Minimum Row Active to Row Active delay (t
RRD
)
Minimum RAS to CAS delay (t
RCD
)
Minimum RAS Pulse width (t
RAS
)
Module Bank Density
Address and Command Setup Time Before Clock
Address and Command Hold Time After Clock
Data Input Setup Time Before Clock
Data Input Hold Time After Clock
Reserved
SPD Revision
See the AC output load circuit in the AC Characteristics section below
cc = Checksum Data byte, 00-FF (Hex)
“R” = Alphanumeric revision code, A-Z, 0-9
rr = ASCII coded revision code byte “R”
yy = Binary coded decimal year code, 00-99 (Decimal) 00-63 (Hex)
ww = Binary coded decimal week code, 01-52 (Decimal) 01-34 (Hex)
ss = Serial number data byte, 00-FF (Hex)
8. For PC-100 applications only.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
09K3606.F38386
8/99
Page 6 of 18
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