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IBM11N1645LB-70J 参数 Datasheet PDF下载

IBM11N1645LB-70J图片预览
型号: IBM11N1645LB-70J
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM Module, 1MX64, 70ns, CMOS, PDMA168]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 31 页 / 344 K
品牌: IBM [ IBM ]
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IBM11N1645L  
IBM11N1735Q  
1M x 64/72 DRAM Module  
Presence Detect (EEPROM) Bus Timing  
tF  
tR  
tHIGH  
tLOW  
SCL  
tSU:STO  
tSU:STA  
tHD:DAT  
tSU:DAT  
tHD:STA  
SDA IN  
tBUF  
tDH  
tAA  
SDA OUT  
acknowledge. If an acknowledge is detected and no  
stop condition is generated by the master, the slave  
will continue to transmit data. If an acknowledge is  
not detected, the slave will terminate further data  
transmissions and await the stop condition to return  
to standby power mode.  
Presence Detect Operation  
Clock and Data Conventions: Data states on the  
SDA line can change only during SCL low. SDA  
state changes during SCL HIGH are reserved for  
indicating start and stop conditions (Figure 1 & Fig-  
ure 2).  
Figure 1. Data Window  
Start Condition: All commands are preceded by the  
start condition, which is a HIGH to LOW transition of  
SDA when SCL is high. The serial PD device contin-  
uously monitors the SDA and SCL lines for the start  
condition and will not respond to any command until  
this condition has been met.  
SCL  
SDA  
Data Stable  
Data  
Change  
Data Stable  
Stop Condition: All communications are terminated  
by a stop condition, which is a LOW to HIGH transi-  
tion of SDA when SCL is HIGH. The stop condition  
is also used to place the serial PD device into  
standby power mode.  
Figure 2. Definition of Start & Stop  
SCL  
SDA  
Acknowledge: Acknowledge is a software conven-  
tion used to indicate successful data transfers. The  
transmitting device, either master or slave, will  
release the bus after transmitting eight bits. During  
the ninth clock cycle the receiver will pull the SDA  
line LOW to acknowledge that it received the eight  
bits of data (Figure 3).  
The PD device will always respond with an acknowl-  
edge after recognition of a start condition and its  
slave address. If both the device and a write opera-  
tion have been selected, The PD device, will respond  
with an acknowledge after the receipt of each subse-  
quent eight bit word. In the read mode the PD device  
will transmit eight bits of data, release the SDA line  
and monitor the line for an  
Stop  
Bit  
Start  
Bit  
Figure 3. Acknowledge Response From Receiver  
SCL from  
Master  
8
9
Data Output  
from Trans  
Data Output  
from Receiver  
Acknowledge  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
50H8035  
SA14-4630-02  
Revised 5/96  
Page 27 of 33  
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