IBM11M4730H
IBM11M4730HB
4M x 72 DRAM MODULE
AC Characteristics (T = 0 to +70°C, V = 3.3V ± 0.3V or 5.0V ± 0.5V)
A
cc
1. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and
VIL.
2. An initial pause of 200µs is required after power-up followed by 8 RAS only refresh cycles before proper device operation is
achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh
cycles is required.
3. The specified timings include buffer, loading and skew delay adders: 2ns minimum, 5ns maximum delay, no pulse shrinkage to the
Dram device timings. The data and RAS signals are not buffered, which preserves the DRAMs access specifications of 60ns and
70ns.
4. AC measurements assume tT = 5ns.
.
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
-60
-70
Symbol
Parameter
Unit
Notes
Min
110
40
10
60
15
5
Max
—
Min
130
50
10
70
20
5
Max
—
tRC
tRP
Random Read or Write Cycle Time
RAS Precharge Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
ns
—
—
tCP
CAS Precharge Time
—
—
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tODD
tDZO
tDZC
tAR
RAS Pulse Width
10K
10K
—
10K
10K
—
CAS Pulse Width
1
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
8
—
8
—
2
—
2
—
10
18
13
20
58
10
20
-2
—
10
18
13
25
68
10
25
-2
—
40
25
—
45
30
—
2
3
CAS Hold Time
—
—
CAS to RAS Precharge Time
OE to DIN Delay Time
—
—
—
—
4
5
5
6
OE Delay Time from DIN
CAS Delay Time from DIN
Column Address Hold Time Referenced to RAS
Transition Time (Rise and Fall)
—
—
-2
—
-2
—
—
3
—
—
3
—
tT
30
30
1. The minimum tCAS requires tCSH to be met for both writes and reads. Also, because of the buffer, the minimum tCAS for a read cycle
must be extended to guarantee the data out window (tOH) in the application. For example, a tCAS of 15ns plus a minimum tOH of 2ns
would result in turning data out of the DIMM at 17ns (3ns before max tCAC of 20ns).
2. Operation within the tRCD(max) limit ensures that tRAC(max) can be met. The tRCD(max) is specified as a reference point only: If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled by tCAC.
3. Operation within the tRAD(max) limit ensures that tRAC(max) can be met. The tRAD(max) is specified as a reference point only: If tRAD
is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
4. Either tCDD or tODD must be satisfied.
5. Either tDZC or tDZO must be satisfied.
6. This timing parameter is not applicable to this product, but applies to a related product in this family.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
54H8529
SA14-4637-01
Released 3/96
Page 7 of 26
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