IBM11M4730H
IBM11M4730HB
4M x 72 DRAM MODULE
Write Cycle (Late Write)
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tRSH
tRCD
tCRP
VIH
CAS
VIL
tCAS
tRAD
tASC
tASR
tRAH
tCAH
tAR
VIH
VIL
Address
Row
Column
tCWL
tWP
tRCS
tWCR
VIH
VIL
WE
OE
tRWL
VIH
VIL
tOEH
tDH
tODD
tDZO
tDS
tDHR
tDZC
VIH
VIL
Valid Data In
DIN
Hi-Z
tOEZ
tCLZ
tOEA
VOH
VOL
Hi-Z*
DOUT
Hi-Z
: “H” or “L” *Output remains Hi-Z because WE is latched internally following t
wp
min.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
54H8529
SA14-4637-01
Released 3/96
Page 14 of 26
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