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IBM0612804GT3B-8N 参数 Datasheet PDF下载

IBM0612804GT3B-8N图片预览
型号: IBM0612804GT3B-8N
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 16MX8, 0.8ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66]
分类和应用: 动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 79 页 / 1362 K
品牌: IBM [ IBM ]
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IBM0612404GT3B  
IBM0612804GT3B  
Advance Rev 0.2  
128Mb Double Data Rate Synchronous DRAM  
Burst Definition  
Starting Column Address  
Order of Accesses Within a Burst  
Burst Length  
A2  
A1  
A0  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Type = Sequential  
Type = Interleaved  
0-1  
0-1  
2
1-0  
1-0  
0
0
1
1
0
0
1
1
0
0
1
1
0-1-2-3  
0-1-2-3  
1-2-3-0  
1-0-3-2  
4
2-3-0-1  
2-3-0-1  
3-0-1-2  
3-2-1-0  
0
0
0
0
1
1
1
1
0-1-2-3-4-5-6-7  
1-2-3-4-5-6-7-0  
2-3-4-5-6-7-0-1  
3-4-5-6-7-0-1-2  
4-5-6-7-0-1-2-3  
5-6-7-0-1-2-3-4  
6-7-0-1-2-3-4-5  
7-0-1-2-3-4-5-6  
0-1-2-3-4-5-6-7  
1-0-3-2-5-4-7-6  
2-3-0-1-6-7-4-5  
3-2-1-0-7-6-5-4  
4-5-6-7-0-1-2-3  
5-4-7-6-1-0-3-2  
6-7-4-5-2-3-0-1  
7-6-5-4-3-2-1-0  
8
Notes:  
1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the  
block.  
2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within  
the block.  
3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access  
within the block.  
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps  
within the block.  
Burst Type  
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as  
the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst  
length, the burst type and the starting column address, as shown in Burst Definition on page 11.  
Read Latency  
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command  
and the availability of the first burst of output data. The latency can be programmed 2 or 2.5 clocks.  
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally  
coincident with clock edge n + m.  
Reserved states should not be used as unknown operation or incompatibility with future versions may result.  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
06K0566.F39350  
5/00  
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