IBM0436A41DLAB IBM0418A41DLAB
IBM0418A81DLAB IBM0436A81DLAB
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
.
Features
• 8Mb: 256K x 36 or 512K x 18 organizations
4Mb: 128K x 36 or 256K x 18 organizations
• 0.25 Micron CMOS technology
• Synchronous pipeline mode of operation with
self-timed late write
• Single differential high-speed transceiver logic
(HSTL) Clock
• +3.3V power supply, ground, 2.1V V
DDQ
, and
1.0V V
REF
• HSTL input and output levels
• Registered addresses, write enables, synchro-
nous select, and data-ins
• Registered outputs
• Common I/O
• Asynchronous output enable
• Synchronous power down input
• Boundary scan using limited set of JTAG 1149.1
functions
• Byte write capability and global write enable
• 7 x 17 bump ball grid array package with SRAM
JEDEC standard pinout and boundary SCAN
order
Description
The 4Mb and 8Mb SRAMs—IBM0436A41DLAB,
IBM0418A41DLAB, IBM0418A81DLAB, and
IBM0436A81DLAB—are synchronous pipeline
mode, high-performance CMOS static random
access memories that are versatile, have wide I/O,
and can achieve 3ns cycle times. Dual differential K
clocks are used to initiate the read/write operation
and all internal operations are self-timed. At the ris-
ing edge of the K clock, all addresses, write-
enables, synchronous select, and data ins are regis-
tered internally. Data outs are updated from output
registers on the next rising edge of the K clock. An
internal write buffer allows write data to follow one
cycle after addresses and controls. The SRAM is
operated with a single +3.3V power supply and is
compatible with HSTL I/O interfaces.
crrh3319.10.fm.00
June 12, 2002
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