IBM04184BSLAC
IBM04364BSLAC
256K x 18 & 128K x 36 Standard Write SRAM
Preliminary
Boundary Scan Order (x18) (PH =Place Holder)
Exit Order
Signal
M2
Bump #
5R
6T
Exit Order
Signal
Bump #
2B
PH1
SA7
1
2
27
28
29
30
31
32
33
34
35
36
37
38
SA12
SA1
3A
3
4P
SA9
3C
4
SA13
SA17
ZZ
6R
5T
SA6
2C
5
SA5
2A
6
7T
DQ9
1D
7
DQ0
DQ3
DQ6
DQ7
SBWa
7P
DQ12
DQ15
DQ16
SBWb
ZQ= 0 (PH)
SS
2E
8
6N
6L
2G
1H
9
10
11
12
7K
3G
4D
5L
K3
K
4L
4E
C=02
13
4K
39
4G
C=12
SW
14
15
16
17
18
19
20
21
22
23
24
25
26
G
4F
6H
7G
6F
7E
6D
6A
6C
5C
5A
6B
5B
3B
40
41
42
43
44
45
46
47
48
49
50
51
4H
4M
2K
1L
DQ8
DQ5
DQ4
DQ2
DQ1
SA14
SA15
SA10
SA16
DQ17
DQ14
DQ13
DQ11
DQ10
SA3
2M
1N
2P
3T
2R
4N
2T
3R
SA4
SA0
PH1
SA11
SA8
SA2
M1
1. Input of PH register connected to VSS
.
2. Balls 4G and 4H are unused C Clock pins in this application.
3. K is inverse of K.
75H4340
July 25, 2000
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 16 of 20
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