IBM04184BSLAC
IBM04364BSLAC
256K x 18 & 128K x 36 Standard Write SRAM
Preliminary
Scan Register Definition
Register Name
Instruction
Bypass
Bit Size x18
Bit Size x36
3
1
3
1
ID
32
51
32
70
Boundary Scan *
* The Boundary Scan chain consists of the following bits:
•
•
•
•
•
36 or 18 bits for Data Inputs depending on x18 or x36 configuration
17 bits for SA0 - SA16 for x36, 18 bits for SA0 - SA17 for x18
4 bits for SBWa - SBWd in x36, 2 bits for SBWa and SBWb in x18
8 bits for K, K, SS, G, SW, ZZ, M1 and M2
5 bits for Place Holders
* K and K clocks connect to a differential receiver that generates a single-ended clock signal. This signal and its inverted value are used
for Boundary Scan sampling.
ID Register Definition
Field Bit Number and Description
Part
Revision Number
(31:28)
Device Density and
Configuration (27:18)
Vendor Definition
(17:12)
Manufacture JEDEC
Code (11:1)
Start Bit
(0)
256K x 18
128K x 36
0001
0001
011 100 1011
011 010 1100
001110
001110
000 101 001 00
000 101 001 00
1
1
Instruction Set
Code
Instruction
SAMPLE-Z
IDCODE
Notes
000
001
010
011
100
101
110
111
1
2
1
5
4
5
5
3
SAMPLE-Z
PRIVATE
SAMPLE
PRIVATE
PRIVATE
BYPASS
1. Places DQs in High-Z in order to sample all input data regardless of other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data.
3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded
TDI when exiting the Shift DR state.
4. SAMPLE instruction does not place DQs in High-Z and does not affect SRAM operation.
5. This instruction is reserved for the exclusive use of IBM. Invoking this instruction may cause improper SRAM functionality.
List of IEEE 1149.1 Standard Violations:
• 7.2.1.b, e
• 7.7.1.a-f
• 10.1.1.b, e
• 10.7.1.a-d
• 6.1.1.d
75H4340
July 25, 2000
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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