IBM043616CBLBC
IBM041816CBLBC
16Mb (512K x 36 & 1M x 18) SRAM
Function Control
The function control is dependent on the state of the three function control pins (B1, B2, and B3), captured
when CK transitions from low to high as described in the following table (“n” refers to the current cycle and
“n-1” refers to the previous SRAM cycle).
B1 (n-1)
X
X
X
X
0
0
0
0
X
1
B2 (n-1)
X
X
X
X
0
0
1
1
X
0
B3 (n-1)
X
X
X
X
0
1
0
1
X
X
B1 (n)
0
0
0
0
1
1
1
1
1
1
B2 (n)
0
0
1
1
1
1
1
1
0
X
B3 (n)
0
1
0
1
X
X
X
X
X
X
Function (n)
Load New Address, Double Data Rate (DDR) Write
Load New Address, Single Data Rate (SDR) Write
Load New Address, DDR Read
Load New Address, SDR Read
Continue Burst, DDR Write
Continue Burst, SDR Write
Continue Burst, DDR Read
Continue Burst, SDR Read
NOP (High-Z cycle n+1)
NOP (High-Z cycle n+2)
Burst Order Definition
The DC state of the LBO pin determines the burst order of the addresses, given the starting address in a
Load operation (B1 = 0). The following table defines the order of addresses for the two different states of
LBO.
Address Sequence when LBO = V
DD
(Interleave Burst)
SA1
Starting address
Second address
Third address
Fourth address
0
0
1
1
SA0
0
1
0
1
SA1
0
0
1
1
SA0
1
0
1
0
SA1
1
1
0
0
SA0
0
1
0
1
SA1
1
1
0
0
SA0
1
0
1
0
Address Sequence when LBO = V
SS
(Linear Burst)
SA1
Starting address
Second address
Third address
Fourth address
0
0
1
1
SA0
0
1
0
1
SA1
0
1
1
0
SA0
1
0
1
0
SA1
1
1
0
0
SA0
0
1
0
1
SA1
1
0
0
1
SA0
1
0
1
0
CBLBCds.fm.00
June 3, 2002
Page 7 of 25
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