IBM043616CBLBC
IBM041816CBLBC
16Mb (512K x 36 & 1M x 18) SRAM
Programmable Impedance Output Driver DC Electrical Characteristics
(TA = 0 to +85°C, VDD = 2.5V ± 5%)
Symbol
Parameter
Min.
Max.
Units
V
Notes
1, 3
VOH
VOL
VDDQ / 2
VDDQ
Output High Voltage
Output Low Voltage
VSS
VDDQ/2
V
2, 3
1.
2.
I
I
OH = (VDDQ / 2) / (RQ / 5) ± 15% @ VOH = VDDQ / 2 (for: 175Ω ≤ RQ ≤ 350Ω).
OL = (VDDQ / 2) / (RQ / 5) ± 15% @ VOL = VDDQ / 2 (for: 175Ω ≤ RQ ≤ 350Ω).
3. Parameter tested with RQ = 250Ω and VDDQ = 1.8 V.
PBGA Thermal Characteristics
Symbol
Parameter
Rating
1
Units
Thermal Resistance Junction to Case
RΘJC
°C/W
Capacitance (TA = 0 to +85°C, VDD = 2.5V ±5%, f = 1MHz)
Symbol
CIN
Parameter
Test Condition
VIN = 0V
Max.
Units
pF
Input Capacitance
Data I/O Capacitance (DQ0–DQ35)
4
5
COUT
VOUT = 0V
pF
AC Input Characteristics (TA = 0 to +85°C, VDD = 2.5V ± 5%)
Symbol
IH (ac)
Parameter
Min.
Max.
Units
mV
Notes
3, 4
V
VREF + 400
AC Input Logic High
AC Input Logic Low
V
IL (ac)
VDIF (ac)
REF (ac)
VREF - 400
mV
mV
mV
3, 4
2, 3
1
Clock Input Differential Voltage
VREF Peak-to-Peak AC Voltage
800
V
5% VREF (dc)
1. The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF
2. SRAM performance is a function of clock input differential voltage (VDIF).
.
3. To guarantee AC characteristics; VIH, VIL, Trise, and Tfall of the inputs and clocks must be within 20% of each other. If these condi-
tions are not met then:
•
Setup time is measured from clock crossing to inputs at their switched VIHAC, VILAC levels.
•
Hold time is measured from clock crossing to inputs switching out of their valid VIHAC, VILAC levels.
4. See AC Test Loading on page 12.
CBLBCds.fm.00
June 3, 2002
Page 11 of 25
IBM [ IBM ]
