.
IBM043616CBLBC
IBM041816CBLBC
16Mb (512K x 36 & 1M x 18) SRAM
Features
• 512K x 36 or 1M x 18 organization
• CMOS technology
• Double-data-rate and single-data-rate synchro-
nous mode of operation
• Pipeline mode of operation
• Self-timed late write with full data coherency
• Single differential clock
• 1.8V high-speed transceiver logic (HSTL) I/O
•
2.5V power supply, 1.8V V
DDQ
• Registered addresses, controls, and data-ins
• Burst mode of operation
• Common I/O
• Asynchronous output enable
• Boundary scan using a limited set of JTAG
1149.1 functions
• 9 x 17 bump ball grid array package with SRAM
JEDEC standard pinout and boundary SCAN
order
• Programmable impedance output driver
Description
The IBM043616CBLBC and IBM041816CBLBC
16Mb SRAMs are synchronous pipeline-mode, high-
performance CMOS static random-access memo-
ries that have wide I/O and achieve 2.2ns cycle
times. Single differential CK clocks are used to ini-
tialize the read/write operation, and all internal oper-
ations are self-timed. At the rising edge of the CK
clock, addresses and controls are registered inter-
nally. Data-outs are updated from output registers
on the next rising and falling edges of the CK clock,
hence the double data rate. Internal write buffers
allow write data to follow one cycle after addresses
and controls. The SRAM is operated with a single
2.5V power supply and is compatible with HSTL I/O
interfaces.
CBLBCds.fm.00
June 3, 2002
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