IBM0418A8CFLBB IBM0436A8CFLBB
IBM0418A4CFLBB IBM0436A4CFLBB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Preliminary
Clock Truth Table
CK
L→H
L→H
L→H
L→H
L→H
L→H
B1(n)
L
L
L
L
H
H
B2(n)
H
H
L
L
L
H
B3 (n)
H
L
H
L
X
X
DQ (n)
X
X
X
X
X
DQ (n+1)
D
out
0-35
D
out
0-35a
D
IN
0-35
D
IN
0-35a
High-Z
DQ (n+1.5)
Previous Data
held
D
out
0-35b
X
D
IN
0-35b
High-Z
MODE
Read Cycle SDR
Read Cycle DDR
Write Cycle SDR
Write Cycle DDR
NOP (Deselect) Cycle
Continue Burst Operation
Output Enable Truth Table
Operation (n, n+1)
Read
Read
Write (B2 = L)
Deselect (NOP) (B1 = H,B2 = L))
G (n)
L
H
X
X
DQ (n)
D
OUT
0-35
High-Z
X
X
DQ (n+1)
D
OUT
0-35
High-Z
High-Z
High-Z
Absolute Maximum Ratings
Item
Power Supply Voltage
Input Voltage
DQ Input Voltage
Output Supply Voltage
Operating Temperature
Junction Temperature
Storage Temperature
Short Circuit Output Current
Symbol
V
DD
V
IN
V
DQIN
V
DDQ
T
A
T
J
T
STG
I
OUT
Rating
-0.5 to 2.825
-0.5 to 4.3
-0.5 to 2.825
-0.5 to 2.825
0 to 85
110
-55 to +125
25
Units
V
V
V
V
°C
°C
°C
mA
Notes
1
1
1
1
1
1
1
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
2. Excludes DQ inputs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
cddrh251620.07
12/00
Page 8 of 26
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