IBM0418A4ACLAA IBM0418A8ACLAA
IBM0436A8ACLAA IBM0436A4ACLAA
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Scan Register Definition
Register Name
Bit Size x18
Bit Size x36
3
3
1
Instruction
1
Bypass
32
51
32
70
ID
Boundary Scan *
* The Boundary Scan chain consists of the following bits:
•
•
•
•
•
36 or 18 bits for Data Inputs, depending on x18 or x36 configuration
18 bits for SA0 - SA17 in x36, 19 bits for SA0 - SA18 in x18
4 bits for SBWa - SBWd in x36, 2 bits for SBWa and SBWb in x18
9 bits for K, K, ZQ, SS, G, SW, ZZ, M1 and M2
3 bits for Place Holders for 8 Mb, 4bits for Place Holders for 4Mb
* K and K clocks connect to a differential receiver that generates a single-ended clock signal. This signal and its inverted value are used
for Boundary Scan sampling.
ID Register Definition
Field Bit Number and Description
Part
Revision
Number (31:28)
Device Density and
Configuration (27:18)
Vendor Definition
(17:12)
Manufacturer JEDEC
Code (11:1)
Start
Bit(0)
011 010 1011
011 100 1100
101 111 0100
101 101 0011
xxxxxx
xxxxxx
xxxxxx
xxxxxx
000 101 001 00
000 101 001 00
000 101 001 00
000 101 001 00
1
1
1
1
128K x 36
256K x 18
512K x 18
256K x 36
0001
0001
0001
0001
trlh3320.04
01/01
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Use is further subject to the provisions at the end of this document.
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