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IBM0418A41QLAB-3 参数 Datasheet PDF下载

IBM0418A41QLAB-3图片预览
型号: IBM0418A41QLAB-3
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 256KX18, 1.7ns, CMOS, PBGA119, BGA-119]
分类和应用: 静态存储器
文件页数/大小: 26 页 / 141 K
品牌: IBM [ IBM ]
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IBM0418A81QLAB IBM0436A81QLAB  
IBM0418A41QLAB IBM0436A41QLAB  
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM  
IEEE 1149.1 TAP and Boundary Scan  
The SRAM provides a limited set of JTAG functions intended to test the interconnection between SRAM I/Os  
and printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the  
RAM core.  
In conformance with IEEE Standard 1149.1, the SRAM contains a TAP controller, Instruction register, Bound-  
ary Scan register, Bypass register, and ID register.  
The TAP controller has a standard 16-state machine that resets internally upon power-up; therefore, TRST  
signal is not required.  
Signal List  
• TCK: Test Clock  
• TMS: Test Mode Select  
• TDI: Test Data In  
• TDO: Test Data Out  
JTAG DC Operating Characteristics (TA = 0 to +85°C)  
Operates with JEDEC Standard JESD8A (3.3V) logic signal levels  
Parameter  
JTAG Input High Voltage  
JTAG Input Low Voltage  
JTAG Output High Level  
JTAG Output Low Level  
Symbol  
Min.  
2.2  
-0.3  
2.4  
Typ.  
Max.  
V + 0.3  
DD  
Units  
Notes  
1
V
V
V
V
V
IH1  
V
1
0.8  
IL1  
V
1, 2  
1, 3  
OH1  
V
0.4  
OL1  
1. All JTAG inputs and outputs are LVTTL compatible only.  
2. I  
-|8mA|.  
OH1  
OL1  
3. I  
+|8mA|.  
JTAG AC Test Conditions (TA = 0 to +85°C, VDD = 3.3V -5%, +10%)  
Parameter  
Input Pulse High Level  
Symbol  
Conditions  
3.0  
Units  
V
V
IH1  
V
Input Pulse Low Level  
0.0  
V
IL1  
T
Input Rise Time  
2.0  
ns  
ns  
V
R1  
T
Input Fall Time  
2.0  
F1  
Input and Output Timing Reference Level  
1.5  
crrh3316.08  
12/00  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
Page 16 of 26  
 
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