IBM041811TLAB
IBM043611TLAB
Preliminary
32K x 36 & 64K x 18 SRAM
Revision Log
Revision
3/96
Contents of Modification
Initial release of the 32K x 36 & 64K x 18 (4/5/6) BGA PIPELINE Application Spec.
Add OEM P/Ns.
4/96
C
(3->4pF), C
(4->5pF),
IN
OUT
Input leakage conditions (V = V ->V ),
IH
-max
IN
DD
Output leakage current conditions (V
= V ->V
),
7/96
OUT
DD
DDQ
AC Input levels( V = 0->0.25V, V = 1.5->1.25V),
IL
IH
Diff Clk Voltage (V
= 0.75->1.0V).
DIF-CLK
Add Caution on page 14:
TCK, TMS, TDI inputs must be biased to a valid logic level, even if JTAG is not used
See AC Characteristics on page 11:
12/96
1) t
2) t
3) t
= 1.75 -> 2.0ns.
= 1.75 -> 2.0ns.
= 4 -> 8ns, 5 -> 10ns, 6 -> 12ns.
GHQZ
GLQV
ZZE
2/97
6/97
Corrected part numbers.
See AC Characteristics on page 11:
1) Add 7ns sort.
2) t
3) t
= 1.0 -> 0.75ns for 4N ns sort
= 1.0 -> 0.75ns for 4N ns sort.
KHAX
KHDX
See AC Characteristics on page 11:
1) For sorts 6 and 7, T = 1.0 and is guaranteed by test.
9/97
KHQX
2) t
= 0.5 -> 0.3ns.
GLQX
Change Revision A to Revision B.
See AC Characteristics on page 11:
1) Add 4ns sort.
10/98
2) Change JTAG ID Register Definition on page 18.
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Use is further subject to the provisions at the end of this document.
77H9965.T5
10/98
Page 21 of 22
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