Discontinued (12/98 - last order; 9/99 last ship)
.
IBM0316409C
IBM0316169C
IBM03164B9C
16Mb Synchronous DRAM-Die Revision D
IBM0316809C
Features
• High Performance:
-80
CL=3
-360
CL=3
-10
CL=3
• Multiple Burst Read with Single Write Option
Units
MHz
ns
ns
• Automatic and Controlled Precharge Command
• Data Mask for Read/Write control (x4, x8)
• Dual Data Mask for byte control (x16)
• Auto Refresh (CBR), Self Refresh (SR)
f
CK
Clock Frequency
t
CK
Clock Cycle
t
AC
Clock Access Time
125
8
6
100
10
5.5
100
10
8
• Suspend Mode and Power Down Mode
• Single Pulsed RAS Interface
• Fully Synchronous to Positive Clock Edge
• Dual Banks controlled by A11 (Bank Select)
• Programmable CAS Latency: 1,2,3
• Programmable Burst Length: 1,2,4,8,full-page
• Programmable Wrap Sequence: Sequential or
Interleave
• 4096 refresh cycles/64ms
• Random Column Address every CLK (1-N Rule)
• Single 3.3V
±
0.3V Power Supply
• Supports LVTTL I/O interface
• Package: 44 pin 400 mil TSOP-Type II (x4,x8)
50 pin 400 mil TSOP-Type II (x16)
2-High Stack TSOJ
Description
IBM’s 0316409C, 0316809C, and 0316169C
are dual bank Synchronous DRAMs organized as
2Mbit x 4 I/O x 2 Bank, 1Mbit x 8 I/O x 2 Bank, and
512Kbit x 16 I/O x 2 Bank, respectively. These
devices support LVTTL I/O interface levels.
A
stacked version of the x 4 component is also
offered. These synchronous devices achieve high
speed data transfer rates of up to 125 MHz. The
chip is fabricated with IBM’s advanced 16Mbit
CMOS DRAM process technology.
The device is designed to comply with all
JEDEC standards set for synchronous DRAM prod-
ucts, both electrically and mechanically. All of the
control, address and data input/output circuits are
synchronized with the positive edge of an externally
supplied clock (CLK).
Internal chip operating modes are defined by
combinations of RAS, CAS, WE, and CS and a com-
mand decoder initiates the necessary timings for
each operation. A twelve bit address bus accepts
address data in the conventional RAS/CAS multi-
plexing style. Eleven row addresses (A0-A10) and a
bank select address (A11) are strobed with RAS.
Ten column addresses (A0-A9) plus A10 and a bank
select address (A11) are strobed with CAS. Column
08J3348.E35853
5/98
address A9 is dropped on the x8 device and column
addresses A8 and A9 are dropped on the x16
device. Access to the lower or upper DRAM in a
stacked device is controlled by CS0 and CS1.
Prior to any access operation, the CAS latency,
burst length, and burst sequence must be pro-
grammed into the device by address inputs A0-A11
during a mode register set cycle. In addition, it is
possible to program a multiple burst sequence with
single write cycle for write through cache operation.
Operating the two memory banks in an inter-
leave fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
125 MHz is possible depending on burst length,
CAS latency, and speed grade of the device.
Auto Refresh (CBR) and Self Refresh (SR)
operation are supported. Refreshing both decks of a
stacked device simultaneously is allowed during
Self Refresh but all other stacked device operations
must be performed on a single deck at a time.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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