IBM0316409C IBM0316809C
IBM0316169C
16Mbit Synchronous DRAM
Bank Activate Command
In relation to the operation of a fast page mode DRAM, the Bank Activate command corresponds to a falling
RAS signal. The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the
rising edge of the clock. The bank select address, A11 (sometimes referred to as BS), is used to select the
desired bank. If BS is low then bank A is activated, if BS is high then bank B is activated. The row address A0
- A10 is used to determine which row to activate in the selected bank.
The Bank Activate command must be applied before any Read or Write operation can be executed. The
delay from when the Bank Activate command is applied to when the first read or write operation can begin
must meet or exceed the RAS to CAS delay time (tRCD). Once a bank has been activated it must be pre-
charged before another Bank Activate command can be applied to the same bank. The minimum time inter-
val between successive Bank Activate commands to the same bank is determined by the RAS cycle time of
the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B
and vice versa) is the Bank to Bank delay time (tRRD).
Bank Activate Command Cycle (CAS latency = 3)
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
CLK
. . . . . . . . . .
Bank A
Col. Addr.
Bank A
Row Addr.
Bank B
Row Addr.
Bank A
Row Addr.
. . . . . . . . . .
ADDRESS
RAS-CAS delay (tRCD
)
RAS - RAS delay time (tRRD
)
Write A
with Auto
Precharge
Bank B
Activate
Bank A
Activate
Bank A
Activate
. . . . . . . . . .
NOP
NOP
NOP
NOP
COMMAND
: “H” or “L”
RAS Cycle time (tRC
)
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS
high and CAS low at the clock’s rising edge after the necessary RAS to CAS delay (tRCD). WE must also be
defined at this time to determine whether the access cycle is a read operation (WE high), or a write operation
(WE low).
The SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a
serial read or write operation on successive clock cycles at data rates of up to 100MHz. The number of serial
data bits for each access is equal to the burst length, which is programmed into the Mode Register. Although
the burst length is user programmable, the boundary of the burst cycle is restricted to specific segments of
the page length.
For example, the 2Mbit x 4 I/O x 2 Bank device has a page length of 1024 bits (defined by CA0-CA9). If a
burst length of 4 is programmed into the Mode Register, then 256 boundary segments (4-bits each) are
addressable. The first access will begin at the column address supplied to the device during the READ or
Write Command (CA0-CA9). However, the second access is not necessarily the next higher order column
address. The second access is a function of the starting address, the burst sequence, and burst boundary.
Restated, the burst sequence is contained to four bits associated with one of the 256 possible boundary seg-
ments. The actual boundary segment (1 of 256) is determined by the eight higher order column addresses
(CA2-CA9). The first access within this boundary segment is determined by the two low order column
addresses (CA0-CA1) and the following three accesses are determined by the burst sequence.
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
07H3997
SA14-4711-02
Revised 05/96
Page 11 of 100
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