IBM0316409C IBM0316809C
IBM0316169C
16Mbit Synchronous DRAM
Block Diagram (512Kbit x 16 I/O x 2 Bank)
Row Decoder
Row Decoder
Row Decoder
Row Decoder
2048 x 512
Memory Bank A
2048 x 256
Memory Bank A
CKE
CKE Buffer
Self
Refresh Clock
2048
16
512
1024
256
1024
Row
Address
Counter
Bank A
Row/Column
Select
16
CLK
CLK Buffer
16
11
Predecode A
Sequential
Control
Bank A
8
8
8
8
Data Latches
Data Latches
Data Latches
Data Latches
16
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11 (BS)
Address Buffers (12)
12
3
8
12
11
Mode Register
8
CS
CS Buffer
3
Sequential
Control
Bank B
16
Data Latches
Data Latches
11
Predecode B
8
Command Decoder
RAS
RAS Buffer
Bank B
Row/Column
Select
16
Column Decoder and DQ Gate
Column Decoder and DQ Gate
Sense Amplifiers
16
Sense Amplifiers
256
CAS
CAS Buffer
WE
WE Buffer
Row Decoder
Row Decoder
Row Decoder
Row Decoder
2048
Memory Bank B
Memory Bank B
2048 x B
Memory Bank 256
2048 x 1024
Memory Bank B
2048 x 512
2048 x 1024
UDQM
DQM Buffer
LDQM
DQM Buffer
07H3997
SA14-4711-02
Revised 05/96
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 100
Data Input/Output Buffers
Sense Amplifiers
Sense Amplifiers
Sense Amplifiers
Column Decoder andAmplifiers
Sense DQ Gate
Column Decoder and DQ Gate
Column Decoder and DQ Gate
Column Decoder and DQ Gate
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
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