Discontinued (8/98 - last order; 12/98 last ship)
IBM0164165B
IBM0164165P
4M x 16 13/9 EDO DRAM
Revision Log
Revision
1/2/97
Contents of Modification
Initial specification release.
1. WE for the Hidden Refresh Write cycle in the Truth Table was changed from “H” to “L”.
2. tOED was moved from the Common Parameters table to the Write Cycle Parameters Table.
3. The note “Implementing WE at RAS time during a Read or Write cycle is optional. Doing so will facilitate
compatibility with future EDO DRAMs.” was removed from all of the Read and Write timing diagrams.
4. tODD was changed to tOED in notes in the Write Cycle and Read Cycle Parameters tables.
5. “Hyper Page Mode” was changed to “EDO (Hyper Page) Mode” in the timing diagram titles.
6. Removed the Test Mode parameters and timing diagrams.
7. LVTTL/LVCMOS changed to TTL/CMOS.
03/19/97
8. LVCMOS currents were removed.
9. Power numbers on the spec cover were recalculated.
11/97
1. Changed Retention Time from 256ms to 128ms on Low Power DRAMs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
88H2012
GA14-4251-02
Revised 11/97
Page 27 of 28
IBM [ IBM ]
