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IBM014405PJ1-60 参数 Datasheet PDF下载

IBM014405PJ1-60图片预览
型号: IBM014405PJ1-60
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM, 1MX4, 60ns, CMOS, PDSO20, 0.300 INCH, PLASTIC, SOJ-26/20]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 30 页 / 340 K
品牌: IBM [ IBM ]
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IBM014405M IBM014405  
IBM014405P IBM014405B  
1M x 4 10/10 EDO DRAM  
AC Characteristics (T =0 to +70°C)  
A
1. An initial pause of 100µs is required after power-up followed by 8 RAS only refresh cycles or 8 CAS before RAS refresh cycles.  
2. AC measurements assume tT=2ns.  
3. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH  
and VIL (or between VIL and VIH).  
4. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in  
a monotonic manner.  
5. If OE is tied permanently low, Late-Write or Read-Modify-Write operations are not possible.  
6. If both RAS and CAS = VIH, then the data I/O’s will be high impedance.  
7. If CAS = VIL, then the data I/O’s may contain data from the last valid Read cycle.  
8. Measured with a load equivalent to 2 TTL loads and 100pF.  
Read, Write, Read-Modify-Write and Ref. Cycles (Common Parameters)  
-60  
-70  
Symbol  
Parameter  
Units  
Notes  
Min.  
104  
40  
10  
60  
10  
0
Max.  
Min.  
124  
50  
10  
70  
12  
0
Max.  
tRC  
tRP  
Random Read or Write Cycle Time  
RAS Precharge Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCP  
CAS Precharge Time  
1
tRAS  
tCAS  
tASR  
tRAH  
tASC  
tCAH  
tRCD  
tRAD  
tRSH  
tCSH  
tCRP  
tOED  
tDZO  
tDZC  
tT  
RAS Pulse Width  
10K  
10K  
10K  
10K  
CAS Pulse Width  
Row Address Setup Time  
Row Address Hold Time  
Column Address Setup Time  
Column Address Hold Time  
RAS to CAS Delay Time  
RAS to Column Address Delay Time  
RAS Hold Time  
10  
0
10  
0
10  
14  
12  
10  
50  
5
10  
14  
12  
12  
55  
5
45  
30  
50  
35  
2
3
CAS Hold Time  
CAS to RAS Precharge Time  
OE to DIN Delay Time  
15  
0
15  
0
4
5
5
6
OE Delay Time From DIN  
CAS Delay Time From DIN  
Transition Time (Rise and Fall)  
0
0
2
30  
2
30  
1. If CAS is Low at the falling edge of RAS, data will be maintained from the previous cycle. To initiate a new cycle and clear the I/O  
buffers, CAS must be pulsed High for tCP  
2. Operation within the tRCD(max) limit ensures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is  
greater than the specified tRCD(max) limit, then access time is controlled by tCAC  
3. Operation within the tRAD(max) limit ensures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is  
.
.
greater than the specified tRAD(max) limit, then access time is controlled by tAA  
4. Either tCDD or tOED must be satisfied.  
.
5. Either tDZC or tDZO must be satisfied.  
6. AC measurements assume tT=2ns.  
©IBM Corporation, 1996. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
27H6242  
SA14-4232-03  
Revised 6/96  
Page 6 of 29  
 
 
 
 
 
 
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