IBM014405
IBM014405M
IBM014405B IBM014405P
1M x 4 10/10 EDO DRAM
DC Electrical Characteristics (T = 0 to +70˚C, V = 3.3V ± 0.3V or V = 5.0V ± 0.5V)
A
CC
CC
3.3 Volt Device 5.0 Volt Device
Symbol
Parameter
Units Notes
Min.
—
Max.
95
Min.
—
Max.
85
Operating Current
ICC1 Average Power Supply Operating Current
(RAS and CAS Cycling: tRC = tRC min.)
-60
-70
mA
mA
mA
mA
mA
mA
µA
1,2,3,4
4
—
—
—
—
—
—
—
—
—
—
—
80
2.0
1.0
95
—
—
—
—
—
—
—
—
—
—
—
70
2.0
1.0
85
Standby Current (TTL)
ICC2 Power Supply Standby Current
(RAS = CAS ≥ VIH min)
SP version
LP version
-60
RAS Only Refresh Current
ICC3 Average Power Supply Current, RAS Only Mode
(RAS Cycling, CAS ≥ VIH min: tRC = tRC min)
1,3,4
1,2,3
5, 6
-70
80
70
Extended Data Out (Hyper Page) Mode Current
ICC4 Average Power Supply Current, EDO Mode
(RAS = VIL min, CAS Cycling, tHPC = tHPC min)
-60
65
60
-70
65
60
Standby Current (CMOS)
ICC5 Power Supply Standby Current
(RAS = CAS ≥ VIH)
SP version
LP version
-60
1.0
0.15
95
1.0
0.15
85
CAS Before RAS Refresh Current
ICC6 Average Power Supply Current, CAS Before RAS Mode
(RAS Cycling, CAS before RAS, tRC = tRC min)
1,3,4,7
5,6
-70
80
70
Self Refresh Current, LP version only
ICC7 Average Power Supply Current during Self Refresh
(CBR cycle with RAS ≥ tRASS (min))
—
—
—
170
300
5
—
—
—
170
300
5
Battery Backup Refresh Current, LP version only
Average Power Supply Current during Battery Backup refresh
ICC8
µA
5,6,8
4,9
(CAS ≤VIL, WE ≥VIH, tRAS ≤ 1µSec, tRC=125µSec)
Standby Current
ICC9 Standby current with Output’s enabled
mA
(RAS ≥ VIH (min) and CAS ≤ VIL (max))
Input Leakage Current, any input
(0.0 ≤ VIN ≤ (VCC + 1.0V)) for 5.0V, or
(0.0 ≤ VIN ≤ (VCC + 0.3V)) for 3.3V. All Other Pins Not Under Test = 0V
II(L)
µA
µA
V
-10
-10
2.4
+10
+10
VCC
-10
-10
2.4
+10
+10
VCC
Output Leakage Current
(DOUT is disabled, 0.0 ≤ VOUT ≤ VCC max)
IO(L)
Output Level (TTL)
VOH Output “H” Level Voltage
(IOUT = -5mA for 5.0V, or IOUT = -2mA for 3.3V)
Output Level (TTL)
Output “L” Level Voltage
VOL
0.0
0.4
0.0
0.4
V
(IOUT = +4.2mA for 5.0V, or IOUT = +2mA for 3.3V)
1. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open.
3. Column address can be changed once or less while RAS =VIL and CAS =VIH.
4. All I/O and other input pins must be ≤ VIL(max) or ≥VIH(min).
5. ((VCC-0.2V ≤ VIH ≤ VCC+0.5V) and (0.0V ≤ VIL ≤ 0.2V)) for 5.0V, or ((VCC-0.2V ≤ VIH ≤ VCC+0.3V) and (0.0V ≤ VIL ≤ 0.2V)) for 3.3V.
6. All other I/O and other inputs at VIH or VIL.
7. Enables on-chip refresh and address counters.
8. 1024 rows at 128µs = 128ms.
9. Assumes no resistive loads on I/O pins.
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
27H6242
SA14-4232-03
Revised 6/96
Page 5 of 29
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