IBM014405
IBM014405M
IBM014405B IBM014405P
1M x 4 10/10 EDO DRAM
Block Diagram
I/O0
I/O1
I/O2
I/O3
VSS
VCC
4
4
Data In
Buffer
Data Out
Buffer
OE
WE
&
4
4
CAS Clock
Generator
CAS
Column Address
Buffer (10)
10
4
10
Column Decoder and I/O Gate
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Sense Amplifiers
1024 x 4
Refresh
Controller
Refresh Counter
(10)
Memory
Array
1024
1024 x 1024 x 4
10
10
Row Address
Buffer (10)
10
RAS Clock
Generator
RAS
Truth Table
Row
Col.
Function
RAS
CAS
WE
OE
I/O0 - I/O3
Address Address
H→X
L
Standby
H
X
H
X
L
X
X
High Impedance
Data Out
Read
L
Row
Row
Row
Row
Row
N/A
Row
N/A
Row
N/A
Row
X
Col.
Col.
Col.
Col.
Col.
Col.
Col.
Col.
Col.
Col.
N/A
N/A
Early-Write
Delayed-Write
Read-Modify-Write
L
L
L
X
Data In
H→L
H→L
L
L
H
Data In
L→H
L
L
Data Out, Data In
Data Out
H→L
H→L
H→L
H→L
H→L
H→L
H
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
L
H
H
L
L
Extended Data Out (Hyper Page)
Mode Read
L
Data Out
L
L
X
Data In
Extended Data Out (Hyper Page)
Mode Write
L
L
L
X
Data In
H→L
H→L
X
L→H
L→H
X
Data Out, Data In
Data Out, Data In
High Impedance
High Impedance
Extended Data Out (Hyper Page)
Mode Read-Modify-Write
L
RAS-Only Refresh
L
H→L
CAS-Before-RAS Refresh
Hidden Refresh Read
L
H
X
L
L
H
L
Row
X
Col.
X
Data Out
X
L→H→L
H→L
Self Refresh (LP version only)
L
H
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
27H6242
SA14-4232-03
Revised 6/96
Page 3 of 29
IBM [ IBM ]
