IBM0117805 IBM0117805M
IBM0117805B IBM0117805P
2M x 8 11/10 EDO DRAM
Revision Log
Revision
Contents Of Modification
11/15/95
Initial Release
1. The Low Power and Standard Power Specifications were combined. ES# 43G9060 and ES# 28H4724 were
combined into ES# 28H4724.
2. Added Die Rev E part numbers.
3. A -6R speed sort was added, with the following differences over the -60 speed sort:
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tCAC was increased from 15ns to 17ns for the -6R speed sort
tRCD (max) was decreased from 45ns to 43ns for the -6R speed sort.
tCWD was increased from 34ns to 36ns for the -6R speed sort.
tOEA was increased from 15ns to 17ns for the -6R speed sort.
12/10/95
4. tCHD was added to the Self Refresh Cycle with a value of 350µs for all speed sorts.
5. The Self Refresh timing diagram was changed to allow CAS to go high tCHD (350µs) after RAS falls entering a
Self Refresh.
6. The CBR timing diagram was changed to allow CAS to remain low for back-to-back CBR cycles.
7. WE for the Hidden Refresh Write cycle in the Truth Table was changed from “L” to ” H”.
1. ICC2 was changed from 2mA to 1mA.
2. II(L) and IO(L) were altered from +/- 10uA to +/- 5uA.
3. tRC was changed from 89ns to 84ns for the -50 speed sort.
4. tCSH changed from 45ns to 38ns, 50ns to 45ns, and 55ns to 50ns for the -50, -60, and -70 speed sorts, respec-
tively.
5. tT was initially at a max of 30ns. It has been modified to 50ns for all speed sorts.
6. tCPA was decreased from 30ns to 28ns for the -50 speed sort.
7. tRASP max of 125K was raised to 200K for all speed sorts.
8. tOEP was changed from 10ns to 5ns for all speed sorts.
09/01/96
9. tOEHC was also lowered from 10ns to 5ns for all speed sorts.
10. tRP was changed from 35ns to 30ns for the -50 speed sort.
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28H4724
SA14-4221-04
Revised 11/96
Page 29 of 29
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